专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6100128A Process for making six-transistor SRAM cell local interconnect structure 有权
标题翻译：制造六晶体管SRAM单元局部互连结构的工艺
公开(公告)号：US6100128A
公开(公告)日：2000-08-08
申请号：US129254
申请日：1998-08-04
申请人： Pailu Wang , Chuen-Der Lien , Kyle W. Terrill
发明人： Pailu Wang , Chuen-Der Lien , Kyle W. Terrill
IPC分类号： G11C11/412 , H01L27/11 , H01L21/8238
CPC分类号： G11C11/412 , H01L27/1104 , Y10S257/903
摘要： A patterned planarized insulating layer and a patterned metal layer form all local interconnects required within six-transistor SRAM cells. Supply voltage and ground lines are formed in the metal layer or in a separate layer to maximize available wiring area. Local interconnect size is maximized to increase node capacitance within the cells and reduce soft error rates, and supply voltage and ground wiring area is maximized for added cell stability and static noise margin improvement. Openings in the insulating layer for contacts, including local interconnects, bit lines, supply voltage and ground contacts, are formed with a single mask and self-aligned contact etch. Line size and spacing for the patterned metal layer is minimized because surface contours do not disturb masking and etching and all openings are formed using a single mask. The metal layer can be made thin so that the layers overlying the interconnect layer are nearly flat and so bonding pads in the metal layer are eliminated. In one embodiment, the metal layer that includes a glue layer and a plug layer and is etched to remove the plug layer from above the surface of the insulating layer. This leaves the glue layer for forming the local interconnects.
摘要翻译：图形化的平坦化绝缘层和图案化金属层形成六晶体管SRAM单元内所需的所有局部互连。在金属层或单独的层中形成电源电压和接地线以最大化可用的布线面积。局部互连尺寸最大化以增加单元内的节点电容并降低软错误率，并且为增加的单元稳定性和静态噪声容限提高，电源电压和接地布线面积最大化。用于接触的绝缘层中的开口，包括局部互连，位线，电源电压和接地触点，用单个掩模和自对准接触蚀刻形成。图案化金属层的线尺寸和间距最小化，因为表面轮廓不会妨碍掩模和蚀刻，并且使用单个掩模形成所有开口。可以使金属层变薄，使得覆盖在互连层上的层几乎是平坦的，因此消除了金属层中的接合焊盘。在一个实施例中，包括胶层和插塞层的金属层被蚀刻以从绝缘层的表面上方移除插塞层。这留下用于形成局部互连的胶层。

2. 发明授权

US5831899A Local interconnect structure and process for six-transistor SRAM cell 失效
标题翻译：用于六晶体管SRAM单元的局部互连结构和工艺
公开(公告)号：US5831899A
公开(公告)日：1998-11-03
申请号：US841985
申请日：1997-04-07
申请人： Pailu Wang , Chuen-Der Lien , Kyle W. Terrill
发明人： Pailu Wang , Chuen-Der Lien , Kyle W. Terrill
IPC分类号： G11C11/412 , H01L27/11 , G11C11/00
CPC分类号： G11C11/412 , H01L27/1104 , Y10S257/903
摘要： A patterned planarized insulating layer and a patterned metal layer form all local interconnects required within six-transistor SRAM cells. Supply voltage and ground lines are formed in the metal layer or in a separate layer to maximize available wiring area. Local interconnect size is maximized to increase node capacitance within the cells and reduce soft error rates, and supply voltage and ground wiring area is maximized for added cell stability and static noise margin improvement. Openings in the insulating layer for contacts, including local interconnects, bit lines, supply voltage and ground contacts, are formed with a single mask and self-aligned contact etch. Line size and spacing for the patterned metal layer is minimized because surface contours do not disturb masking and etching and all openings are formed using a single mask. The metal layer can be made thin so that the layers overlying the interconnect layer are nearly flat and so that bonding pads in the metal layer are eliminated. In one embodiment, the metal layer includes a glue layer and a plug layer and is etched to remove the plug layer from above the surface of the insulating layer. This leaves the glue layer for forming the local interconnects.
摘要翻译：图形化的平坦化绝缘层和图案化金属层形成六晶体管SRAM单元内所需的所有局部互连。在金属层或单独的层中形成电源电压和接地线以最大化可用的布线面积。局部互连尺寸最大化以增加单元内的节点电容并降低软错误率，并且为增加的单元稳定性和静态噪声容限提高，电源电压和接地布线面积最大化。用于接触的绝缘层中的开口，包括局部互连，位线，电源电压和接地触点，用单个掩模和自对准接触蚀刻形成。图案化金属层的线尺寸和间距最小化，因为表面轮廓不会妨碍掩模和蚀刻，并且使用单个掩模形成所有开口。可以使金属层变薄，使得覆盖在互连层上的层几乎是平的，并且消除金属层中的接合焊盘。在一个实施例中，金属层包括胶层和塞层，并被蚀刻以从绝缘层的表面上方移除塞子层。这留下用于形成局部互连的胶层。

3. 发明授权

US5789314A Method of topside and inter-metal oxide coating 失效
标题翻译：顶部和金属间氧化物涂层的方法
公开(公告)号：US5789314A
公开(公告)日：1998-08-04
申请号：US567648
申请日：1995-12-05
申请人： Chu-Tsao Yen , Shih-Ked Lee , Tong Zhang , Pailu Wang , Chuen-Der Lien
发明人： Chu-Tsao Yen , Shih-Ked Lee , Tong Zhang , Pailu Wang , Chuen-Der Lien
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76837 , Y10S438/945
摘要： A method is provided for suppressing or eliminating void formation during the manufacture of integrated circuits. TEOS is deposited and etched to form recesses that assist in eliminating or suppressing void formation. The recesses may be located in an interlevel layer, or within the oxide layer just beneath the passivation layer.
摘要翻译：提供了在集成电路制造期间抑制或消除空隙形成的方法。沉积和蚀刻TEOS以形成有助于消除或抑制空隙形成的凹陷。凹陷可以位于层间层中，或位于钝化层正下方的氧化物层内。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式