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1. 发明授权

US06459296B2 Method, system and method of using a component for setting the electrical characteristics of microelectronic circuit configurations 有权
标题翻译：使用组件设置微电子电路配置的电气特性的方法，系统和方法
公开(公告)号：US06459296B2
公开(公告)日：2002-10-01
申请号：US09916668
申请日：2001-07-26
申请人： Stephan Bradl , Oliver Gehring , Olaf Heitzsch
发明人： Stephan Bradl , Oliver Gehring , Olaf Heitzsch
IPC分类号： H03K19177
CPC分类号： G11C27/005
摘要： The electrical characteristic of a microelectronic circuit configuration that has at least one analog electronic unit is set. In a configuration step, by feeding and/or extracting electrical charge, the analog electronic unit is put into a state which permanently determines the analog electrical characteristics of the unit. In particular, the floating gate of an EEPROM cell is charged up to a freely selectable charge value lying within a continuous range.
摘要翻译：设置具有至少一个模拟电子单元的微电子电路配置的电气特性。在配置步骤中，通过馈送和/或提取电荷，模拟电子单元处于永久确定单元的模拟电气特性的状态。特别地，EEPROM单元的浮置栅极被充电至可连续范围内的可自由选择的电荷值。

2. 发明申请

US20100320613A1 INTEGRATED CIRCUIT ARRANGEMENT WITH AN AUXILIARY INDENTATION, PARTICULARLY WITH ALIGNING MARKS 有权
标题翻译：集成电路与辅助电路的布置，特别是符号标记
公开(公告)号：US20100320613A1
公开(公告)日：2010-12-23
申请号：US12854676
申请日：2010-08-11
申请人： Klaus Goller , Olaf Heitzsch , Marion Nichterwitz
发明人： Klaus Goller , Olaf Heitzsch , Marion Nichterwitz
IPC分类号： H01L23/48 , H01L23/544
CPC分类号： G03F9/7084 , G03F7/70633 , G03F9/7076 , G03F9/708 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit arrangement is disclosed having a wiring indentation and an auxiliary indentation in a dielectric layer. The wiring indentation contains a metal through which current flows during operation of the circuit arrangement. The auxiliary indentation contains a metal through which an electric current does not flow during operation of the circuit arrangement. The auxiliary indentation serves as an alignment mark during the production of the integrated circuit arrangement.
摘要翻译：公开了在电介质层中具有布线压痕和辅助压痕的集成电路装置。布线压痕包含在电路布置操作期间电流流动的金属。辅助压痕包含在电路布置操作期间电流不流过的金属。在制造集成电路装置期间，辅助压痕用作对准标记。

3. 发明授权

US06447372B1 Polishing agent for semiconductor substrates 有权
标题翻译：半导体衬底抛光剂
公开(公告)号：US06447372B1
公开(公告)日：2002-09-10
申请号：US09491296
申请日：2000-01-25
申请人： Stephan Bradl , Olaf Heitzsch
发明人： Stephan Bradl , Olaf Heitzsch
IPC分类号： B24B100
CPC分类号： C09K3/1463
摘要： The polishing agent of the invention has polishing grains suspended in a solution. The polishing grains consist essentially of a first substance with a glass transition temperature TG, and the polishing grains contain a dopant. The concentration of the dopant is set so that the glass transition temperature TG′ of the doped substance is lower than the glass transition temperature TG of the undoped first substance. The polishing agent is advantageously used for the microscratch-free planarization of a semiconductor substrate or of layers applied on it.
摘要翻译：本发明的抛光剂具有悬浮在溶液中的抛光颗粒。抛光颗粒基本上由具有玻璃化转变温度TG的第一物质组成，并且抛光颗粒含有掺杂剂。掺杂剂的浓度设定为使得掺杂物质的玻璃化转变温度TG'低于未掺杂的第一物质的玻璃化转变温度TG。抛光剂有利地用于半导体衬底或其上施加的层的无显微镜的平面化。

4. 发明授权

US07795105B2 Method for producing an integrated circuit assembly with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement 有权
标题翻译：用于制造具有辅助压痕的集成电路组件的方法，特别是对准标记，以及集成电路装置
公开(公告)号：US07795105B2
公开(公告)日：2010-09-14
申请号：US11527736
申请日：2006-09-25
申请人： Klaus Goller , Olaf Heitzsch , Marion Nichterwitz
发明人： Klaus Goller , Olaf Heitzsch , Marion Nichterwitz
IPC分类号： H01L21/76
CPC分类号： G03F9/7084 , G03F7/70633 , G03F9/7076 , G03F9/708 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method is disclosed for producing an integrated circuit arrangement with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement. The invention also relates to a method for producing aligning marks. During the method, a planarization is carried out before material is removed from an auxiliary indentation.
摘要翻译：公开了用于制造具有辅助压痕的集成电路装置的方法，特别是对准标记，以及集成电路装置。本发明还涉及一种生产对准标记的方法。在该方法期间，在从辅助压痕移除材料之前进行平坦化。

5. 发明授权

US06337255B1 Method for forming a trench structure in a silicon substrate 有权
标题翻译：在硅衬底中形成沟槽结构的方法
公开(公告)号：US06337255B1
公开(公告)日：2002-01-08
申请号：US09535648
申请日：2000-03-24
申请人： Stephan Bradl , Olaf Heitzsch , Michael Schmidt
发明人： Stephan Bradl , Olaf Heitzsch , Michael Schmidt
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/76229 , Y10S438/969
摘要： A method for forming a trench structure in a silicon substrate, which trench structure serves for electrically insulating a first region of the substrate from a second substrate region. The method proceeds from a growth of a thermal oxide layer on the substrate surface and an application and patterning of a mask layer over the thermal oxide layer. A trench of predetermined depth is subsequently etched into the silicon substrate through the patterned mask layer. The trench is filled by a deposition of a conformal covering oxide layer on the substrate with an essentially uniform thickness that is sufficient for completely filling the trench. Afterwards, a polysilicon layer is deposited on the covering oxide layer and a chemical mechanical planarization method is carried out with high selectivity S between the polysilicon material and the oxide material in order to obtain a flat surface. In a further method step, the layer is additionally removed by an essentially nonselective, joint etching of the polysilicon material and of the oxide material while maintaining a planar surface produced in the preceding planarization step. The etching operation is carried out at least until all the polysilicon material has been removed in a region of the trench.
摘要翻译：一种用于在硅衬底中形成沟槽结构的方法，该沟槽结构用于将衬底的第一区域与第二衬底区域电绝缘。该方法从衬底表面上的热氧化物层的生长和在氧化物层上的掩模层的施加和图案化开始。随后通过图案化掩模层将预定深度的沟槽蚀刻到硅衬底中。通过在衬底上沉积保形覆盖的氧化物层来填充沟槽，其厚度足以完全填充沟槽。之后，在覆盖氧化物层上沉积多晶硅层，并且在多晶硅材料和氧化物材料之间以高选择性S进行化学机械平面化方法以获得平坦表面。在另一种方法步骤中，通过基本上非选择性的多晶硅材料和氧化物材料的接合蚀刻来另外除去该层，同时保持在前面的平坦化步骤中产生的平坦表面。蚀刻操作至少直到在沟槽的区域中已经除去所有多晶硅材料为止。

6. 发明授权

US08901737B2 Integrated circuit arrangement with an auxiliary indentation, particularly with aligning marks 有权
标题翻译：具有辅助压痕的集成电路布置，特别是对准标记
公开(公告)号：US08901737B2
公开(公告)日：2014-12-02
申请号：US12854676
申请日：2010-08-11
申请人： Klaus Goller , Olaf Heitzsch , Marion Nichterwitz
发明人： Klaus Goller , Olaf Heitzsch , Marion Nichterwitz
IPC分类号： H01L23/48 , G03F9/00 , G03F7/20 , H01L23/544
CPC分类号： G03F9/7084 , G03F7/70633 , G03F9/7076 , G03F9/708 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit arrangement is disclosed having a wiring indentation and an auxiliary indentation in a dielectric layer. The wiring indentation contains a metal through which current flows during operation of the circuit arrangement. The auxiliary indentation contains a metal through which an electric current does not flow during operation of the circuit arrangement. The auxiliary indentation serves as an alignment mark during the production of the integrated circuit arrangement.
摘要翻译：公开了在电介质层中具有布线压痕和辅助压痕的集成电路装置。布线压痕包含在电路布置操作期间电流流动的金属。辅助压痕包含在电路布置操作期间电流不流过的金属。在制造集成电路装置期间，辅助压痕用作对准标记。

7. 发明申请

US20070102819A1 Method for producing an integrated circuit assembly with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement 有权
标题翻译：用于制造具有辅助压痕的集成电路组件的方法，特别是对准标记，以及集成电路装置
公开(公告)号：US20070102819A1
公开(公告)日：2007-05-10
申请号：US11527736
申请日：2006-09-25
申请人： Klaus Goller , Olaf Heitzsch , Marion Nichterwitz
发明人： Klaus Goller , Olaf Heitzsch , Marion Nichterwitz
IPC分类号： H01L23/544 , H01L21/4763
CPC分类号： G03F9/7084 , G03F7/70633 , G03F9/7076 , G03F9/708 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method is disclosed for producing an integrated circuit arrangement with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement. The invention also relates to a method for producing aligning marks. During the method, a planarization is carried out before material is removed from an auxiliary indentation.
摘要翻译：公开了用于制造具有辅助压痕的集成电路装置的方法，特别是对准标记，以及集成电路装置。本发明还涉及一种生产对准标记的方法。在该方法期间，在从辅助压痕移除材料之前进行平坦化。

8. 发明授权

US06645812B2 Method for fabricating a non-volatile semiconductor memory cell with a separate tunnel window 有权
公开(公告)号：US06645812B2
公开(公告)日：2003-11-11
申请号：US10033949
申请日：2001-12-28
申请人： Peter Wawer , Oliver Springmann , Konrad Wolf , Olaf Heitzsch , Kai Huckels , Reinhold Rennekamp , Mayk Röhrich , Elard Stein Von Kamienski , Christoph Kutter , Christoph Ludwig
发明人： Peter Wawer , Oliver Springmann , Konrad Wolf , Olaf Heitzsch , Kai Huckels , Reinhold Rennekamp , Mayk Röhrich , Elard Stein Von Kamienski , Christoph Kutter , Christoph Ludwig
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L29/7883
摘要： A method for producing a non-volatile semiconductor memory cell with a separate tunnel window cell includes the step of forming a tunnel zone in a late implantation step by performing a tunnel implantation with the aid of a tunnel window cell as a mask. The resulting memory cell has a small area requirement and a high number of program/clear cycles.

9. 发明授权

US6014218A Device and method for end-point monitoring used in the polishing of components, in particular semiconductor components 有权
标题翻译：用于组件，特别是半导体部件的抛光中的端点监视的装置和方法
公开(公告)号：US6014218A
公开(公告)日：2000-01-11
申请号：US204785
申请日：1998-12-03
申请人： Stephan Bradl , Olaf Heitzsch
发明人： Stephan Bradl , Olaf Heitzsch
IPC分类号： B24B37/013 , B24B37/20 , B24B49/12 , H01L21/306 , H01L21/66 , G01B11/06 , G01B11/30
CPC分类号： H01L22/26 , B24B37/013 , B24B37/205 , B24B49/12
摘要： A device for end-point monitoring used in the polishing of components, in particular semiconductor components. The device has a textile structure, which may be constructed as a cloth or a pad, and is used to accommodate a component that is to be monitored. The textile-like structure has a windowless construction. The textile structure may be disposed on a platen. Furthermore, a light source, preferably a laser, for emitting a monochromatic red light beam having a preferred wavelength of approximately 800 nm is provided. The red light beam is directed through the textile structure onto the component to be monitored. In addition, a detector is used to detect the red light beam reflected by the component to be monitored. The end-point monitoring may, for example, be carried out by interferometry. In addition, a corresponding method is also described.
摘要翻译：用于组件，特别是半导体部件的抛光中的端点监视装置。该装置具有纺织结构，其可以构造成布或垫，并且用于容纳待监测的部件。纺织样结构具有无窗构造。织物结构可以设置在台板上。此外，提供了用于发射具有大约800nm的优选波长的单色红色光束的光源，优选地是激光器。红色光束通过纺织结构被引导到待监测的部件上。此外，使用检测器来检测被监视部件反射的红色光束。例如，终点监视可以通过干涉测量来进行。此外，还描述了相应的方法。

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