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1. 发明授权

US5809552A Data processing system, memory access device and method including selecting the number of pipeline stages based on pipeline conditions 失效
标题翻译：数据处理系统，存储器访问装置和方法，包括基于流水线条件选择流水线级数
公开(公告)号：US5809552A
公开(公告)日：1998-09-15
申请号：US705562
申请日：1996-08-29
申请人： Koichi Kuroiwa , Hideyuki Iino , Hiroyuki Fujiyama , Kenji Shirasawa , Masaharu Kimura , Noriko Kadomaru , Shinichi Utsunomiya , Makoto Miyagawa
发明人： Koichi Kuroiwa , Hideyuki Iino , Hiroyuki Fujiyama , Kenji Shirasawa , Masaharu Kimura , Noriko Kadomaru , Shinichi Utsunomiya , Makoto Miyagawa
IPC分类号： G06F13/16 , G06F13/00
CPC分类号： G06F13/1615
摘要： A memory accessing device and method, in a data processing system which has pipelines, for correctly associating prefetched addresses from an address bus with corresponding prefetched data from a data bus, when sending data to and receiving data from an external memory. The memory accessing device has a condition determining device determining pipeline control conditions based on pipeline information and address information; a number-of-stages selecting device selecting the number of pipeline stages based on pipeline activation conditions and the pipeline control conditions; and a valid data detecting device detecting valid data positions in the prefetched data based on the number of pipeline stages selected and correctly associating the valid data positions in the prefetched data with the prefetched addresses. Additionally, a data input/output unit performs an arithmetic operation on data transferred from an external memory to a vector register, wherein the result of the arithmetic operation, upon completion, is transferred from the vector register to the external memory for storage. The data input/output unit has a data holding unit storing m-bit data units and rearranges exactly in the original order n pieces of m/n-bit data when n pieces of m/n-bit data are loaded from an external memory and then stored back into the external memory.
摘要翻译：一种具有管线的数据处理系统中的存储器访问装置和方法，用于当从外部存储器发送数据并从外部存储器接收数据时，将来自地址总线的预取地址与来自数据总线的相应预取数据正确地相关联。所述存储器访问装置具有根据流水线信息和地址信息确定流水线控制条件的条件判定装置; 阶段选择装置，其基于流水线激活条件和流水线控制条件选择流水线级数; 以及有效数据检测装置，基于所选择的流水线级数，并将预取数据中的有效数据位置与预取地址正确地相关联，来检测预取数据中的有效数据位置。此外，数据输入/输出单元对从外部存储器传送到向量寄存器的数据执行算术运算，其中算术运算的结果在完成后从矢量寄存器传送到外部存储器用于存储。数据输入/输出单元具有存储m位数据单元的数据保持单元，并且当从外部存储器加载n个m / n位数据时，以原始顺序重新排列n个m / n位数据，然后存储回外部存储器。

2. 发明申请

US20070038795A1 Asynchronous bus interface and processing method thereof 审中-公开
标题翻译：异步总线接口及其处理方法
公开(公告)号：US20070038795A1
公开(公告)日：2007-02-15
申请号：US11289477
申请日：2005-11-30
申请人： Noriko Kadomaru
发明人： Noriko Kadomaru
IPC分类号： G06F13/36 , G06F1/12
CPC分类号： G06F13/36 , G06F13/4059 , Y02D10/14 , Y02D10/151
摘要： An asynchronous bus interface which is capable of securing a sufficient access effective period and eliminating a useless access wait time even when a frequency of a clock changes is provided. An asynchronous bus interface having an input part which inputs therein frequency information of a clock of a synchronous device which operates synchronously with the clock, and a signal generating part which generates a second access signal based on a first access signal when inputting therein the first access signal to an asynchronous device from the synchronous device, and outputs the second access signal to the asynchronous device is provided. The signal generating part determines a number of effective cycles of the second access signal in accordance with the frequency information of the clock.
摘要翻译：一种异步总线接口，其能够确保足够的访问有效期，并且即使在提供时钟变化的频率时也消除无用的访问等待时间。一种异步总线接口，具有输入部，其输入与时钟同步的同步装置的时钟的频率信息;以及信号生成部，其在输入第一存取时基于第一存取信号生成第二存取信号提供来自同步装置的异步装置的信号，并将第二接入信号输出到异步装置。信号生成部根据时钟的频率信息来决定第二存取信号的有效周期数。

3. 发明授权

US5644748A Processor system including an index buffer circuit and a translation look-aside buffer control circuit for processor-to-processor interfacing 失效
标题翻译：处理器系统包括索引缓冲器电路和用于处理器到处理器接口的翻译后备缓冲器控制电路
公开(公告)号：US5644748A
公开(公告)日：1997-07-01
申请号：US11761
申请日：1993-02-01
申请人： Shinichi Utsunomiya , Hideyuki Iino , Noriko Kadomaru , Makoto Miyagawa
发明人： Shinichi Utsunomiya , Hideyuki Iino , Noriko Kadomaru , Makoto Miyagawa
IPC分类号： G06F9/38 , G06F12/10
CPC分类号： G06F12/1027 , G06F9/3824
摘要： An index buffer circuit and a translation look-aside buffer (TLB) are provided in an address unit of a vector processor unit. The index buffer circuit incudes a plurality of buffers, an input pointer generating unit for generating an input control signal indicating which selected buffer in a buffer portion, index data shall be stored, and an output pointer generating unit for outputting a control signal indicated from which selected buffer in the buffer portion output data is to be read. The TLB translates a logical address to a physical address upon receipt of the output from the index buffer. The TLB has a least recently used (LRU) flag register which can maintain the priority even if the entries are reset and thus the entries of the TLB can be used as buffers when the vector processor unit operates as a bus slave.
摘要翻译：在矢量处理器单元的地址单元中提供索引缓冲器电路和平移后备缓冲器（TLB）。索引缓冲器电路包括多个缓冲器，输入指针产生单元，用于产生指示缓冲器部分中的哪个选择的缓冲器，索引数据将被存储的输入控制信号;以及输出指针产生单元，用于输出指示的控制信号要读取缓冲区输出数据中的选定缓冲区。 TLB在接收到索引缓冲区的输出时将逻辑地址转换为物理地址。 TLB具有最近最少使用的（LRU）标志寄存器，其即使条目被复位也可以保持优先级，因此当矢量处理器单元作为总线从机时，TLB的条目可以用作缓冲器。

4. 发明授权

US5742842A Data processing apparatus for executing a vector operation under control of a master processor 失效
标题翻译：数据处理装置，用于在主处理器的控制下执行向量操作
公开(公告)号：US5742842A
公开(公告)日：1998-04-21
申请号：US601704
申请日：1996-02-15
申请人： Seiji Suetake , Hideyuki Iino , Koichi Hatta , Tatsuya Nagasawa , Koichi Kuroiwa , Hiroyuki Fujiyama , Kenji Shirasawa , Noriko Kadomaru , Shinichi Utsunomiya , Makoto Miyagawa
发明人： Seiji Suetake , Hideyuki Iino , Koichi Hatta , Tatsuya Nagasawa , Koichi Kuroiwa , Hiroyuki Fujiyama , Kenji Shirasawa , Noriko Kadomaru , Shinichi Utsunomiya , Makoto Miyagawa
IPC分类号： G06F9/38 , G06F15/78
CPC分类号： G06F9/3887 , G06F15/8053 , G06F9/30036 , G06F9/3877
摘要： A slave processor for executing for example a vector operation is connected to a master processor. A vector length for a vector operation set to the slave processor can be changed without intervention of the master processor. When the master processor activates the slave processor, the slave processor outputs a busy signal immediately (at most one cycle later). The master processor reads the value of a busy register representing a busy/ready status of the slave processor in a slave access cycle at highest speed (in two cycles at most). Regardless of whether the master processor and the slave processor was designed as series products or general purpose products, they can be effectively connected.
摘要翻译：用于执行例如向量操作的从属处理器连接到主处理器。可以在没有主处理器干预的情况下改变设置到从属处理器的向量操作的向量长度。当主处理器激活从属处理器时，从属处理器立即输出忙信号（最多一个周期）。主处理器以最高速度（最多两个周期）在从站访问周期中读取表示从属处理器的忙/就绪状态的忙寄存器的值。无论主处理器和从属处理器是设计为系列产品还是通用产品，都可以有效连接。

5. 发明授权

US5596294A Synchronizing circuit for dividing a frequency of a clock signal supplied from an external device into a plurality of internal clock signals 失效
标题翻译：用于将从外部设备提供的时钟信号的频率分成多个内部时钟信号的同步电路
公开(公告)号：US5596294A
公开(公告)日：1997-01-21
申请号：US492311
申请日：1995-06-19
申请人： Noriko Kadomaru , Fumitaka Asami
发明人： Noriko Kadomaru , Fumitaka Asami
IPC分类号： H04N5/06 , G06F1/06 , G06F1/12 , H03K5/00 , H03L7/00 , H03K1/04
CPC分类号： H03K5/00006 , G06F1/06 , G06F1/12 , H03L7/00
摘要： A synchronizing circuit has a first signal generating unit for dividing a control signal to obtain a first signal having a first frequency, a second signal generating unit for dividing the control signal to obtain a second signal having a second frequency, a third signal generating unit for dividing the control signal to obtain a third signal having a third frequency and synchronized with the second signal, and a synchronizing signal generating unit for generating a synchronizing signal which is adapted to synchronize the first signal with the second and third signals in accordance with a logical operation on the first, second and third signals. With this arrangement, the internal clock signals can be synchronized without using a reset signal. Consequently, neither wiring for supplying the reset signal nor a circuit for generating the reset signal are necessary.
摘要翻译：同步电路具有用于分割控制信号以获得具有第一频率的第一信号的第一信号产生单元，用于分配控制信号以获得具有第二频率的第二信号的第二信号产生单元，用于分配控制信号以获得具有第三频率并与第二信号同步的第三信号，以及同步信号产生单元，用于产生适于使第一信号与第二和第三信号同步的同步信号，该同步信号根据逻辑对第一，第二和第三信号进行操作。利用这种布置，可以在不使用复位信号的情况下同步内部时钟信号。因此，不需要用于提供复位信号的布线和用于产生复位信号的电路。

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