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1. 发明授权

US08049304B2 Constructions comprising hafnium oxide and/or zirconium oxide 有权
标题翻译：包含氧化铪和/或氧化锆的构造
公开(公告)号：US08049304B2
公开(公告)日：2011-11-01
申请号：US12422788
申请日：2009-04-13
申请人： Cancheepuram V. Srividya , Noel Rocklein , John Vernon , Jeff Nelson , F. Daniel Gealy , David Korn
发明人： Cancheepuram V. Srividya , Noel Rocklein , John Vernon , Jeff Nelson , F. Daniel Gealy , David Korn
IPC分类号： H01L29/92
CPC分类号： C23C16/405 , C23C16/40 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02194 , H01L21/022 , H01L21/0228 , H01L21/3141 , H01L21/3162 , H01L21/31641 , H01L21/31645 , H01L28/40
摘要： The invention includes ALD-type methods in which two or more different precursors are utilized with one or more reactants to form a material. In particular aspects, the precursors are hafnium and aluminum, the only reactant is ozone, and the material is hafnium oxide predominantly in a tetragonal crystalline phase.
摘要翻译：本发明包括ALD型方法，其中使用两种或更多种不同的前体与一种或多种反应物形成材料。在特定方面，前体是铪和铝，唯一的反应物是臭氧，并且该材料主要是四方晶相中的铪氧化物。

2. 发明申请

US20110220989A1 Memory Cells, Methods Of Forming Dielectric Materials, And Methods Of Forming Memory Cells 有权
标题翻译：记忆细胞，形成介电材料的方法和形成记忆细胞的方法
公开(公告)号：US20110220989A1
公开(公告)日：2011-09-15
申请号：US13116401
申请日：2011-05-26
申请人： D. V. Nirmal Ramaswamy , Noel Rocklein , Kyu S. Min
发明人： D. V. Nirmal Ramaswamy , Noel Rocklein , Kyu S. Min
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/7881 , H01L29/513 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/792
摘要： Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material, crystalline ultra-high k dielectric material over the charge-retaining region, and a control gate material over the crystalline ultra-high k dielectric material. Additionally, the memory cells may include an amorphous region between the charge-retaining region and the crystalline ultra-high k dielectric material, and/or may include an amorphous region between the crystalline ultra-high k dielectric material and the control gate material. Some embodiments include methods of forming memory cells which contain an amorphous region between a charge-retaining region and a crystalline ultra-high k dielectric material, and/or which contain an amorphous region between a crystalline ultra-high k dielectric material and a control gate material.
摘要翻译：一些实施例包括存储器单元。存储单元可以包括隧道电介质材料，隧道电介质材料上方的电荷保持区域，电荷保持区域上的结晶超高k电介质材料，以及结晶超高k电介质材料上的控制栅极材料。此外，存储器单元可以包括电荷保持区域和结晶超高k电介质材料之间的非晶区域，和/或可以包括晶体超高k电介质材料和控制栅极材料之间的非晶区域。一些实施例包括形成在电荷保持区域和结晶超高k电介质材料之间形成非晶区域的存储单元的方法，和/或在晶体超高k电介质材料和控制栅极之间包含非晶区域的方法材料。

3. 发明申请

US20110020999A1 Methods of Forming Dielectric Material-Containing Structures 有权
标题翻译：形成含介电材料的结构的方法
公开(公告)号：US20110020999A1
公开(公告)日：2011-01-27
申请号：US12895535
申请日：2010-09-30
申请人： Noel Rocklein , Chris M. Carlson , Dave Peterson , Cunyu Yang , Praveen Vaidyanathan , Vishwanath Bhat
发明人： Noel Rocklein , Chris M. Carlson , Dave Peterson , Cunyu Yang , Praveen Vaidyanathan , Vishwanath Bhat
IPC分类号： H01L21/02 , H01L21/31 , H01L21/283
CPC分类号： H01L21/28273 , H01L21/02175 , H01L21/02194 , H01L21/022 , H01L21/0228 , H01L21/3142 , H01L27/10852 , H01L28/40 , H01L28/91 , H01L29/51 , H01L29/513 , H01L29/78
摘要： Some embodiments include dielectric structures. The structures include first and second portions that are directly against one another. The first portion may contain a homogeneous mixture of a first phase and a second phase. The first phase may have a dielectric constant of greater than or equal to 25, and the second phase may have a dielectric constant of less than or equal to 20. The second portion may be entirely a single composition having a dielectric constant of greater than or equal to 25. Some embodiments include electrical components, such as capacitors and transistors, containing dielectric structures of the type described above. Some embodiments include methods of forming dielectric structures, and some embodiments include methods of forming electrical components.
摘要翻译：一些实施例包括电介质结构。这些结构包括彼此直接相对的第一和第二部分。第一部分可以包含第一相和第二相的均匀混合物。第一相可以具有大于或等于25的介电常数，并且第二相可以具有小于或等于20的介电常数。第二部分可以是完全是具有大于或等于20的介电常数的单一组成，等于25.一些实施例包括包含上述类型的电介质结构的电气部件，例如电容器和晶体管。一些实施方案包括形成电介质结构的方法，并且一些实施方案包括形成电组件的方法。

4. 发明申请

US20100315760A1 Capacitors Having Dielectric Regions That Include Multiple Metal Oxide-Comprising Materials 失效
标题翻译：具有包含多种金属氧化物的材料的介电区域的电容器
公开(公告)号：US20100315760A1
公开(公告)日：2010-12-16
申请号：US12483474
申请日：2009-06-12
申请人： Rishikesh Krishnan , John Smythe , Vishwanath Bhat , Noel Rocklein , Bhaskar Srinivasan , Jeff Hully , Chris Carlson
发明人： Rishikesh Krishnan , John Smythe , Vishwanath Bhat , Noel Rocklein , Bhaskar Srinivasan , Jeff Hully , Chris Carlson
IPC分类号： H01G4/10
CPC分类号： H01L28/56 , H01G4/10 , H01L27/108
摘要： Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10−7 amps/cm2 at from −1.1V to +1.1V.
摘要翻译：公开了形成电容器的电容器和方法，其包括内部导电金属电容器电极和外部导电金属电容器电极。电容器电介质区域被容纳在内导电金属电容电极和外导电金属电容器电极之间，并且具有不大于150埃的厚度。公开了厚度和关系的材料的各种组合，其相互之间可以实现和导致电介质区域的介电常数k至少为35，而在-1.1V至-1.0V的范围内漏电流不大于1×10-7Aps / cm 2 + 1.1V。

5. 发明申请

US20090001443A1 NON-VOLATILE MEMORY CELL WITH MULTI-LAYER BLOCKING DIELECTRIC 审中-公开
标题翻译：具有多层阻塞介质的非易失性存储单元
公开(公告)号：US20090001443A1
公开(公告)日：2009-01-01
申请号：US11771482
申请日：2007-06-29
申请人： Tejas Krishnamohan , Krishna Parat , Kyu Min , Rhett T. Brewer , Thomas M. Graettinger , Nirmal Ramaswamy , M. Noel Rocklein
发明人： Tejas Krishnamohan , Krishna Parat , Kyu Min , Rhett T. Brewer , Thomas M. Graettinger , Nirmal Ramaswamy , M. Noel Rocklein
IPC分类号： H01L29/788
CPC分类号： H01L29/513 , H01L29/40114 , H01L29/40117 , H01L29/42324 , H01L29/4234
摘要： Disclosed is a non-volatile memory cell. The non-volatile memory cell includes a substrate having an active area. A bottom dielectric layer is disposed over the active area of the substrate which provides tunneling migration to the charge carriers towards the active area. A charge storage node is disposed above the bottom dielectric layer. Further, the non-volatile memory cell includes a plurality of top dielectric layers disposed above the charge storage node. Each of the plurality of top dielectric layers can be tuned with a set of attributes for reducing a leakage current through the plurality of top dielectric layers. Over the plurality of top dielectric layers, a control gate is disposed.
摘要翻译：公开了一种非易失性存储单元。非易失性存储单元包括具有有源区的基板。底部电介质层设置在衬底的有源区上方，其向电荷载流子提供隧道迁移到有源区。电荷存储节点设置在底部电介质层的上方。此外，非易失性存储单元包括设置在电荷存储节点上方的多个顶部电介质层。多个顶部电介质层中的每一个可以用一组属性进行调谐，以减少穿过多个顶部电介质层的漏电流。在多个顶部电介质层中，设置有控制栅极。

6. 发明申请

US20080014694A1 Capacitors and methods of forming capacitors 有权
标题翻译：电容器和形成电容器的方法
公开(公告)号：US20080014694A1
公开(公告)日：2008-01-17
申请号：US11488587
申请日：2006-07-17
申请人： Vishwanath Bhat , Noel Rocklein , F. Daniel Gealy
发明人： Vishwanath Bhat , Noel Rocklein , F. Daniel Gealy
IPC分类号： H01L21/8244
CPC分类号： H01L28/60 , Y10T29/417
摘要： A method of forming a capacitor includes forming a conductive first capacitor electrode material comprising TiN over a substrate. TiN of the TiN-comprising material is oxidized effective to form conductive TiOxNy having resistivity no greater than 1 ohm·cm over the TiN-comprising material where x is greater than 0 and y is from 0 to 1.4. A capacitor dielectric is formed over the conductive TiOxNy. Conductive second capacitor electrode material is formed over the capacitor dielectric. Other aspects and implementations are contemplated, including capacitors independent of method of fabrication.
摘要翻译：形成电容器的方法包括在衬底上形成包含TiN的导电的第一电容器电极材料。含TiN材料的TiN被有效氧化，以形成电阻率不大于1欧姆·厘米的导电性TiO 2，其中x越大 0和y为0至1.4。电容器电介质形成在导电TiO 2上。在电容器电介质上形成导电的第二电容器电极材料。考虑了其他方面和实现方式，包括独立于制造方法的电容器。

7. 发明授权

US08236372B2 Methods of forming capacitors having dielectric regions that include multiple metal oxide-comprising materials 失效
标题翻译：形成具有包括多个含金属氧化物的材料的电介质区域的电容器的方法
公开(公告)号：US08236372B2
公开(公告)日：2012-08-07
申请号：US12483455
申请日：2009-06-12
申请人： Rishikesh Krishnan , John Smythe , Vishwanath Bhat , Noel Rocklein , Bhaskar Srinivasan , Jeff Hall , Chris Carlson
发明人： Rishikesh Krishnan , John Smythe , Vishwanath Bhat , Noel Rocklein , Bhaskar Srinivasan , Jeff Hall , Chris Carlson
IPC分类号： B05D5/12
CPC分类号： H01G4/12 , H01G4/1272 , H01G4/33 , H01L28/40
摘要： Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10−7 amps/cm2 at from −1.1V to +1.1V.
摘要翻译：公开了形成电容器的电容器和方法，其包括内部导电金属电容器电极和外部导电金属电容器电极。电容器电介质区域被容纳在内导电金属电容电极和外导电金属电容器电极之间，并且具有不大于150埃的厚度。公开了厚度和关系的材料的各种组合，其相互之间可以实现和导致电介质区域的介电常数k至少为35，而在-1.1V至-1.0V的范围内漏电流不大于1×10-7Aps / cm 2 + 1.1V。

8. 发明授权

US08183110B2 Memory cells, methods of forming dielectric materials, and methods of forming memory cells 有权
标题翻译：记忆单元，介电材料的形成方法以及形成记忆单元的方法
公开(公告)号：US08183110B2
公开(公告)日：2012-05-22
申请号：US13116401
申请日：2011-05-26
申请人： D. V. Nirmal Ramaswamy , Noel Rocklein , Kyu S. Min
发明人： D. V. Nirmal Ramaswamy , Noel Rocklein , Kyu S. Min
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L29/513 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/792
摘要： Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material, crystalline ultra-high k dielectric material over the charge-retaining region, and a control gate material over the crystalline ultra-high k dielectric material. Additionally, the memory cells may include an amorphous region between the charge-retaining region and the crystalline ultra-high k dielectric material, and/or may include an amorphous region between the crystalline ultra-high k dielectric material and the control gate material. Some embodiments include methods of forming memory cells which contain an amorphous region between a charge-retaining region and a crystalline ultra-high k dielectric material, and/or which contain an amorphous region between a crystalline ultra-high k dielectric material and a control gate material.
摘要翻译：一些实施例包括存储器单元。存储单元可以包括隧道电介质材料，隧道电介质材料上方的电荷保持区域，电荷保持区域上的结晶超高k电介质材料，以及结晶超高k电介质材料上的控制栅极材料。此外，存储器单元可以包括电荷保持区域和结晶超高k电介质材料之间的非晶区域，和/或可以包括晶体超高k电介质材料和控制栅极材料之间的非晶区域。一些实施例包括形成在电荷保持区域和结晶超高k电介质材料之间形成非晶区域的存储单元的方法，和/或在晶体超高k电介质材料和控制栅极之间包含非晶区域的方法材料。

9. 发明授权

US08110469B2 Graded dielectric layers 有权
标题翻译：梯度介电层
公开(公告)号：US08110469B2
公开(公告)日：2012-02-07
申请号：US11216542
申请日：2005-08-30
申请人： Dan Gealy , Vishwanath Bhat , Cancheepuram V. Srividya , M. Noel Rocklein
发明人： Dan Gealy , Vishwanath Bhat , Cancheepuram V. Srividya , M. Noel Rocklein
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/31 , H01L21/469
CPC分类号： H01L21/022 , C23C16/45529 , H01L21/02148 , H01L21/02194 , H01L21/0228 , H01L21/28194 , H01L21/3141 , H01L21/3142 , H01L21/31641 , H01L21/31645 , H01L28/40 , H01L28/56 , H01L29/517 , H01L29/78
摘要： Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.
摘要翻译：梯度介电层和制造这种电介质层的方法在各种电子结构中提供电介质以用于广泛的电子设备和系统。在一个实施例中，电介质层相对于跨介电层的掺杂分布而分级。在一个实施例中，电介质层相对于介电层上的晶体结构分布呈梯度分布。在一个实施例中，通过包含测序技术的原子层沉积形成电介质层以产生掺杂的电介质材料。

10. 发明授权

US07968969B2 Electrical components for microelectronic devices 有权
标题翻译：微电子器件的电气部件
公开(公告)号：US07968969B2
公开(公告)日：2011-06-28
申请号：US12502630
申请日：2009-07-14
申请人： Rishikesh Krishnan , Dan Gealy , Vidya Srividya , Noel Rocklein
发明人： Rishikesh Krishnan , Dan Gealy , Vidya Srividya , Noel Rocklein
IPC分类号： H01L21/02
CPC分类号： H01G4/255 , H01L27/10852 , H01L28/65
摘要： Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process.
摘要翻译：用于微电子器件的电气部件和用于形成电气部件的方法。这种方法的一个具体实施方案包括将下面的层沉积到工件上，并在下层上形成导电层。该方法可以通过在导电层上设置介电层来继续。底层是导致电介质层具有比没有底层存在于导电层下方更高的介电常数的材料。例如，下层可以赋予薄膜叠层的结构或另一性质，导致另外的无定形介电层结晶，而不必在将介电层设置在导电层上之后进行单独的高温退火工艺。预期该方法的几个实例对于形成具有高介电常数的介电层非常有用，因为它们避免使用单独的高温退火工艺。

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