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    • 5. 发明授权
    • Check pattern for a semiconductor device
    • 检查半导体器件的图形
    • US06525548B1
    • 2003-02-25
    • US09710597
    • 2000-11-10
    • Nobuya Nishio
    • Nobuya Nishio
    • G01R2708
    • H01L22/34H01L2924/0002H01L2924/00
    • The present invention provides a check pattern for evaluating the result of via openings during fabrication of a semiconductor device. The check pattern uses a Wheatstone bridge circuit so as to eliminate any influence of variation of wiring resistance and/or contact resistance. In the bridge circuit, four terminals are provided, namely first, second, third and fourth terminals. Each of four sides of the bridge circuit is defined by connecting an upper conductor layer including one terminal, a sub-group of via openings belonging to one group, a lower conductor layer, the other sub-group of via openings belonging to the same group, and an upper conductor layer including another terminal.
    • 本发明提供了一种用于在制造半导体器件期间评估通孔开口结果的检查图案。 检查图案使用惠斯通电桥电路,以消除布线电阻和/或接触电阻变化的任何影响。 在桥式电路中,设置有四个端子,即第一,第二,第三和第四端子。 通过连接包括一个端子,属于一个组的通路开口的子组,下部导体层,属于同一组的通孔的另一个子组的上部导体层来限定桥接电路的四个侧面 ,以及包括另一个端子的上导体层。