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    • 1. 发明授权
    • Voltage control type control apparatus capable of achieving correct
control characteristic without increasing interface line number
    • 电压控制型控制装置能够在不增加接口线数的情况下实现正确的控制特性
    • US6081150A
    • 2000-06-27
    • US55766
    • 1998-04-07
    • Tomoya YamauraNobuhiko Watanabe
    • Tomoya YamauraNobuhiko Watanabe
    • H03G3/02H03G1/00H01J19/82
    • H03G1/0088
    • In a control voltage producing apparatus, either a pulse-duration modulation signal or a pulse-width modulation signal, which are generated in response to a digital control signal, is from a first buffer circuit to an averaging circuit so as to be averaged. A power supply voltage is supplied from a first voltage source to this first buffer circuit. Then, the averaged signal is supplied to a control voltage producing circuit for producing a target control voltage. When a control voltage is produced, the same output voltage as that of the first buffer circuit is generated by a second buffer circuit, and then is supplied to the control voltage generating circuit and an operation control circuit. In response to the output voltage derived from the second buffer circuit, the operation control circuit applies the power supply voltage to the control voltage producing circuit so as to cause this control voltage producing circuit to be operable. Also, the control voltage producing circuit uses the output voltage derived from the second buffer circuit as the reference voltage so as to regulate the control voltage. As a consequence, in response to one of the output voltages derived from the second buffer circuit, turning ON/OFF of the control voltage producing circuit can be controlled, and further the reference voltage used to regulate the control voltage can be applied.
    • 在控制电压产生装置中,响应于数字控制信号而产生的脉冲持续时间调制信号或脉冲宽度调制信号从第一缓冲电路到平均电路被平均化。 电源电压从第一电压源提供给该第一缓冲电路。 然后,平均信号被提供给用于产生目标控制电压的控制电压产生电路。 当产生控制电压时,通过第二缓冲电路产生与第一缓冲电路相同的输出电压,然后提供给控制电压产生电路和操作控制电路。 响应于从第二缓冲电路导出的输出电压,操作控制电路将电源电压施加到控制电压产生电路,以使该控制电压产生电路可操作。 此外,控制电压产生电路使用从第二缓冲电路导出的输出电压作为参考电压,以便调节控制电压。 结果,响应于从第二缓冲电路导出的一个输出电压,可以控制控制电压产生电路的接通/断开,并且还可以应用用于调节控制电压的参考电压。
    • 4. 发明授权
    • Time base correcting apparatus
    • 时基校正装置
    • US4398224A
    • 1983-08-09
    • US298522
    • 1981-09-01
    • Nobuhiko Watanabe
    • Nobuhiko Watanabe
    • H04N5/956G11B5/027G11B5/09G11B20/02G11B20/10G11B20/18H04B14/04H04N5/95
    • G11B20/1809G11B20/10527G11B20/18
    • Time base correcting apparatus is provided for a digital signal supplied to such apparatus in the form of successive data blocks with each data block including plural data words. A memory is provided, having plural addressable storage locations, each adapted to store a respective data block. A write address generator generates write-in addresses to address particular storage locations into which the supplied data blocks are written; and an error detector detects whether the supplied data block contains an error. If no error is detected, a write-in circuit writes that data block into the addressed storage location; but if an error is detected, the data block is inhibited from being stored. An error store also is provided to store an error flag which is, for example, reset when the nono-erroneous data block is written into the addressed storage location, and is set when an error in that data block is detected. A read address generator generates read-out addresses to address those storage locations from which storage data blocks are read. When the contents of an addressed storage location are read out, the error flag associated with that data block is set regardless of its actual condition, thereby preventing subsequent re-use of the contents of that addressed storage location in the event that the data block stored therein is not replaced but is attempted to be re-read.
    • 为连续的数据块形式提供给这种装置的数字信号的时基校正装置,每个数据块包括多个数据字。 提供了具有多个可寻址存储位置的存储器,每个存储位置适于存储相应的数据块。 写地址生成器生成写入地址以寻址写入所提供的数据块的特定存储位置; 并且错误检测器检测所提供的数据块是否包含错误。 如果没有检测到错误,写入电路将该数据块写入寻址的存储位置; 但是如果检测到错误,则禁止数据块被存储。 还提供了一个错误存储器来存储错误标志,该错误标志例如在将非错误数据块写入所寻址的存储位置时复位,并且当检测到该数据块中的错误时被设置。 读地址生成器生成读出地址以寻址读取存储数据块的那些存储位置。 当读出寻址的存储位置的内容时,与该数据块相关联的错误标志被设置为与其实际条件无关,从而防止在存储数据块的情况下该寻址的存储位置的内容的后续重新使用 其中没有更换,但尝试重新读取。
    • 5. 发明授权
    • Rotary head type reproducing apparatus
    • 旋转头式再现装置
    • US5521714A
    • 1996-05-28
    • US327482
    • 1994-10-21
    • Masato TanakaNobuhiko Watanabe
    • Masato TanakaNobuhiko Watanabe
    • G11B5/02G11B5/09G11B15/02G11B15/04G11B27/13G11B33/10H04N5/7824
    • G11B27/13G11B15/02G11B15/04G11B33/10G11B2220/90G11B2220/913
    • In a rotary head type reproducing apparatus, such as a digital audio tape recorder (DAT), a display changeover operation, a key scanning operation or a sensor scanning operation is inhibited during the periods T.sub.PB-A, T.sub.PB-B when a rotary head is in contact with a magnetic tape for reproducing signals, and the display changeover operation is performed during time periods T.sub.DS1 to T.sub.DS4 outside of these periods T.sub.PB-A, T.sub.PB-B, while the scanning operations are performed during a time period T.sub.SC. An error rate may be improved because noises due to display changeover or scanning may be eliminated during the time the magnetic head is contacted with the magnetic tape for signal reproduction. The result is that shielding or the like may be eliminated and the display section of switches may be mounted in proximity to the rotary head to reduce the size of weight of the apparatus.
    • 在诸如数字音频磁带录像机(DAT)的旋转磁头型再现装置中,当旋转磁头是旋转磁头是在时间段TPB-A,TPB-B期间,禁止显示切换操作,键扫描操作或传感器扫描操作 与用于再现信号的磁带接触,并且在这些时段TPB-A,TPB-B之外的时间段TDS1至TDS4期间执行显示切换操作,同时在时间段TSC期间执行扫描操作。 可能会改善错误率,因为在磁头与磁带接触以用于信号再现的时间期间可能消除由于显示切换或扫描引起的噪声。 结果是可以消除屏蔽等,并且开关的显示部分可以安装在旋转头附近,以减小装置的重量。
    • 7. 发明授权
    • Digital signal transmitting system
    • 数字信号发射系统
    • US4429390A
    • 1984-01-31
    • US290848
    • 1981-08-07
    • Takenori SonodaNobuhiko WatanabeMasato Tanaka
    • Takenori SonodaNobuhiko WatanabeMasato Tanaka
    • H03M13/00G08C19/28G11B5/09G11B20/12G11B20/18H03M13/27G06F11/10
    • G11B20/1809
    • A digital signal is encoded for error correction, and the encoded digital signal is transmitted in M transmitting paths. The signal to be encoded occurs as N sequences of data words. A plurality n of sequences of error correcting words are generated from respective words of the N sequences delayed by respective different delay times of (D-di) words, where d.sub.i is a whole number associated with an ith one of the n error correcting word sequences. The resulting N data word sequences and n error correcting word sequences are provided with respective different total delay times, so that the total delays of the N sequences differ by an integral number D of words from one another. Blocks of the delayed N data sequences and n error correcting word sequences are formed and the blocks are cyclically distributed among the M transmitting paths. The values of M, N, n, D, and d.sub.i are selected so that the least common multiple of any two values of (d-d.sub.i) is greater than (N+n-1)D; and for any value of (D-di), (d-di) and M are relatively prime. Favorably, M is selected as 2.sup. k, and (D-d.sub.i) is odd.
    • 数字信号被编码用于纠错,并且编码的数字信号在M个发送路径中发送。 待编码的信号以数据字的N个序列发生。 从(D-di)个字的不同延迟时间延迟的N个序列的各个字生成多个n个纠错字序列,其中di是与n个纠错字序列中的第i个相关联的整数 。 所得到的N个数据字序列和n个纠错字序列被提供有相应不同的总延迟时间,使得N个序列的总延迟彼此相差一个单词的整数D。 形成延迟的N个数据序列的块和n个纠错字序列,并且这些块在M个发送路径之间循环地分布。 选择M,N,n,D和di的值,使得(d-di)任意两个值的最小公倍数大于(N + n-1)D; 并且对于(D-di),(d-di)和M的任何值都是相同的。 有利地,选择M为2k,(D-di)为奇数。