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1. 发明专利

JPS58218670A Range finder for obtaining three-dimensional information 失效
标题翻译：用于获取三维信息的范围查找器
公开(公告)号：JPS58218670A
公开(公告)日：1983-12-19
申请号：JP10108182
申请日：1982-06-13
申请人： Naoki Shimizu
发明人： SHIMIZU NAOKI
IPC分类号： G01S5/16 , G01C3/08
CPC分类号： G01C3/08
摘要： PURPOSE:To obtain a range finder which is capable of securing easily and exactly a three-dimensional range and position relation, by comparing the contrast of image pickup picture elements by plural lenses. CONSTITUTION:An image pickup picture element signal by plural lenses 1 is accumulated in a corresponding image pickup device 2 such as a CCD, etc., and contrast based on picture element information of both the devices 2 is compared in a focusing detection device A. Subsequently, the same picture element of different positions of both the devices 2 is decided in accordance with coincidence and dissidence of color information. Different picture elements of relative positions of both the decides 2, which are decided to be same by said device A are superposed by a superposing circuit controlled by a CPU 9, and from the number of moving picture elements, three-dimensional direction and range corresponding to its picture element are decided. In this way, it is possible to obtain a range finder which is capable of securing easily and exactly a three-dimensional range and position relation without making its constitution complicated.
摘要翻译：目的：通过比较多个透镜的图像拾取图像元素的对比度，获得能够容易且准确地确定三维范围和位置关系的测距仪。构成：通过多个透镜1的图像拾取像素信号被累积在诸如CCD等的相应的图像拾取装置2中，并且在聚焦检测装置A中比较基于两个装置2的图像元素信息的对比度。随后，根据颜色信息的一致性和不一致性来确定两个装置2的不同位置的相同图像元素。由所述装置A判定为相同的判定2的相对位置的不同图像元素由由CPU 9控制的叠加电路叠加，并且根据运动像素的数量，三维方向和范围对应决定其图片元素。以这种方式，可以获得能够容易且准确地确定三维范围和位置关系而不使其结构复杂的测距仪。

2. 发明授权

US09613671B2 Nonvolatile random access memory including control circuit configured to receive commands at high and low edges of one clock cycle 有权
公开(公告)号：US09613671B2
公开(公告)日：2017-04-04
申请号：US14692239
申请日：2015-04-21
申请人： Yutaka Shirai , Naoki Shimizu , Kenji Tsuchida , Yoji Watanabe , Ji Hyae Bae , Yong Ho Kim
发明人： Yutaka Shirai , Naoki Shimizu , Kenji Tsuchida , Yoji Watanabe , Ji Hyae Bae , Yong Ho Kim
IPC分类号： G11C8/00 , G11C8/18 , G11C7/12 , G11C8/10 , G11C8/12 , G11C11/16 , G11C7/10
CPC分类号： G11C7/12 , G11C7/1039 , G11C7/222 , G11C8/10 , G11C8/12 , G11C8/18 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C11/1693
摘要： According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.

3. 发明授权

US09530480B2 Semiconductor memory device 有权
公开(公告)号：US09530480B2
公开(公告)日：2016-12-27
申请号：US14864271
申请日：2015-09-24
申请人： Naoki Shimizu , Ji Hyae Bae
发明人： Naoki Shimizu , Ji Hyae Bae
IPC分类号： G11C11/16 , G11C13/00 , G11C7/22 , G11C11/4076 , G11C7/08 , G11C11/409 , G11C11/419 , G11C8/18 , G11C11/56 , G11C7/10 , G11C8/16
CPC分类号： G11C11/1693 , G11C7/08 , G11C7/109 , G11C7/22 , G11C7/222 , G11C8/16 , G11C8/18 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C11/4076 , G11C11/419 , G11C11/5607 , G11C13/0023 , G11C13/004 , G11C13/0061 , G11C13/0069
摘要： A semiconductor memory device is capable of executing a first mode having a first latency and a second mode having a second latency longer than the first latency. The semiconductor memory device includes: a pad unit configured to receive an address and a command from an outside; a first delay circuit configured to delay the address by a time corresponding to the first latency; a second delay circuit including shift registers connected in series and configured to delay the address by a time corresponding to a difference between the first latency and the second latency; and a controller configured to use the first delay circuit and the second delay circuit when executing the second mode.

4. 发明申请

US20160266804A1 MEMORY DEVICE 审中-公开
标题翻译：内存设备
公开(公告)号：US20160266804A1
公开(公告)日：2016-09-15
申请号：US14852398
申请日：2015-09-11
申请人： Naoki SHIMIZU
发明人： Naoki SHIMIZU
IPC分类号： G06F3/06
CPC分类号： G11C11/1673 , G06F13/161 , G11C11/1693 , G11C13/004 , G11C13/0061
摘要： According to one embodiment, a memory device includes a memory area; and a control circuit, in response to a first command, configured to read out data from the memory area without outputting the data to a data line, subsequently, in response to a second command, configured to output the data to the data line, if the first command is not received after receiving an active command, in response to the second command, configured to output the data read out from the memory area to the data line.
摘要翻译：根据一个实施例，存储器装置包括存储区域; 以及控制电路，响应于第一命令，被配置为从存储器区域读出数据而不将数据输出到数据线，随后响应于第二命令将数据输出到数据线，如果在接收到有效命令之后，响应于第二命令，第一命令被配置为将从存储器区域读出的数据输出到数据线。

5. 发明授权

US09443571B2 Semiconductor memory, memory system and method of controlling semiconductor memory 有权
标题翻译：半导体存储器，存储器系统和半导体存储器的控制方法
公开(公告)号：US09443571B2
公开(公告)日：2016-09-13
申请号：US14644152
申请日：2015-03-10
申请人： Naoki Shimizu
发明人： Naoki Shimizu
IPC分类号： G11C7/22 , G11C7/12 , G11C11/16 , G11C29/52 , G11C7/08 , G11C29/04
CPC分类号： G11C11/1677 , G11C7/08 , G11C7/12 , G11C7/22 , G11C11/1655 , G11C11/1657 , G11C11/1675 , G11C11/1693 , G11C29/52 , G11C2029/0411
摘要： According to one embodiment, a semiconductor memory includes a memory area; an error detection circuit which detect an error of first data output from the memory area; and a control circuit which control the memory area and the error detection circuit. When the error is detected in the first data, the control circuit starts precharge of a bit line at a timing when a first period has elapsed from a start of a first operation of the memory area for output of the first data. When the error is not detected in the first data, the control circuit starts the precharge at a timing when a second period has elapsed from the start of the first operation, the second period is shorter than the first period.
摘要翻译：根据一个实施例，半导体存储器包括存储区域; 检测从存储区域输出的第一数据的错误的错误检测电路; 以及控制电路，其控制存储区域和误差检测电路。当在第一数据中检测到错误时，控制电路在从用于输出第一数据的存储区域的第一操作开始经过第一周期的定时开始对位线进行预充电。当在第一数据中未检测到错误时，控制电路在从第一操作开始经过第二周期的时刻开始预充电，第二周期比第一周期短。

6. 发明申请

US20160064061A1 SEMICONDUCTOR MEMORY, MEMORY SYSTEM AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY 有权
标题翻译：半导体存储器，存储器系统和控制半导体存储器的方法
公开(公告)号：US20160064061A1
公开(公告)日：2016-03-03
申请号：US14644152
申请日：2015-03-10
申请人： Naoki SHIMIZU
发明人： Naoki SHIMIZU
IPC分类号： G11C11/16 , G11C29/52 , G11C29/08
CPC分类号： G11C11/1677 , G11C7/08 , G11C7/12 , G11C7/22 , G11C11/1655 , G11C11/1657 , G11C11/1675 , G11C11/1693 , G11C29/52 , G11C2029/0411
摘要： According to one embodiment, a semiconductor memory includes a memory area; an error detection circuit which detect an error of first data output from the memory area; and a control circuit which control the memory area and the error detection circuit. When the error is detected in the first data, the control circuit starts precharge of a bit line at a timing when a first period has elapsed from a start of a first operation of the memory area for output of the first data. When the error is not detected in the first data, the control circuit starts the precharge at a timing when a second period has elapsed from the start of the first operation, the second period is shorter than the first period.
摘要翻译：根据一个实施例，半导体存储器包括存储区域; 检测从存储区域输出的第一数据的错误的错误检测电路; 以及控制电路，其控制存储区域和误差检测电路。当在第一数据中检测到错误时，控制电路在从用于输出第一数据的存储区域的第一操作开始经过第一周期的定时开始对位线进行预充电。当在第一数据中未检测到错误时，控制电路在从第一操作开始经过第二周期的时刻开始预充电，第二周期比第一周期短。

7. 发明授权

US09203991B2 Information processing device, image processing control method, and recording medium storing image processing control program 有权
标题翻译：信息处理装置，图像处理控制方法和存储图像处理控制程序的记录介质
公开(公告)号：US09203991B2
公开(公告)日：2015-12-01
申请号：US14317067
申请日：2014-06-27
申请人： Naoki Shimizu
发明人： Naoki Shimizu
IPC分类号： H04N1/00
CPC分类号： H04N1/00408 , H04N1/00129 , H04N1/00209 , H04N2201/0094
摘要： An information processing device, separate from an image processing apparatus, which controls the image processing apparatus and includes a display unit, a volatile memory store image data, and a nonvolatile memory. The information processing device also includes an image data acquisition unit that acquires image data processed by the image processing apparatus page by page, an image data storage processor that compares the image data acquired by the image data acquisition unit for each page with the image data stored in the volatile memory and to store the image data in either the volatile memory or the nonvolatile memory based on comparison, a display image generator that generates a display image to be displayed on the display unit based on the image data for each page stored in either the volatile memory or the nonvolatile memory, and a display image output controller that displays the display image generated by the display image generator on the display unit.
摘要翻译：与图像处理装置分离的信息处理装置，其控制图像处理装置并且包括显示单元，易失性存储器存储图像数据和非易失性存储器。信息处理装置还包括图像数据获取单元，其逐页地获取由图像处理装置处理的图像数据，图像数据存储处理器，将由每个页面的图像数据获取单元获取的图像数据与存储的图像数据进行比较在易失性存储器中，并且基于比较将图像数据存储在易失性存储器或非易失性存储器中，显示图像生成器基于存储在任一个的每个页面的图像数据生成要显示在显示单元上的显示图像易失性存储器或非易失性存储器，以及显示图像输出控制器，其将由显示图像生成器生成的显示图像显示在显示单元上。

8. 发明授权

US09202640B2 Ceramic electronic component and manufacturing method thereof 有权
标题翻译：陶瓷电子部件及其制造方法
公开(公告)号：US09202640B2
公开(公告)日：2015-12-01
申请号：US13287276
申请日：2011-11-02
申请人： Kota Zenzai , Hisayoshi Omori , Takashi Kanayama , Kiyoyasu Sakurada , Naoki Shimizu , Seiji Katsuta , Shinji Otani
发明人： Kota Zenzai , Hisayoshi Omori , Takashi Kanayama , Kiyoyasu Sakurada , Naoki Shimizu , Seiji Katsuta , Shinji Otani
IPC分类号： H01G4/005 , H01G4/228 , H01G4/06 , H01G13/00 , H01G4/12
CPC分类号： H01G4/30 , H01G4/005 , H01G4/012 , H01G4/12 , H01G4/248 , H01G4/252 , H01G13/006 , H05K3/1283 , H05K3/4664
摘要： A ceramic body includes an inner electrode disposed inside the ceramic body and in which an end portion of the inner electrode extends to a surface of the ceramic body. An electrode layer is formed on the surface of the ceramic body so as to cover the end portion of the inner electrode, the electrode layer including a resin, a first metal filler that contains a first metal component, and a second metal filler that contains a second metal component having a higher melting point than the first metal component. A step of heating the electrode layer is performed to form an electrode including a metal layer that is located on the surface of the ceramic body and that includes the first and second metal components and a metal contained in the inner electrode.
摘要翻译：陶瓷体包括设置在陶瓷体内部的内部电极，内部电极的端部延伸到陶瓷体的表面。在陶瓷体的表面上形成电极层，以覆盖内部电极的端部，包括树脂的电极层，含有第一金属成分的第一金属填料和含有第一金属成分的第二金属填料具有比第一金属成分高的熔点的第二金属成分。执行加热电极层的步骤，以形成包括位于陶瓷体表面上并且包括第一和第二金属成分的金属层和包含在内部电极中的金属的电极。

9. 发明授权

US09171600B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09171600B2
公开(公告)日：2015-10-27
申请号：US14201686
申请日：2014-03-07
申请人： Naoki Shimizu , Ji Hyae Bae
发明人： Naoki Shimizu , Ji Hyae Bae
IPC分类号： G11C11/16 , G11C13/00 , G11C7/22 , G11C11/4076 , G11C7/08 , G11C11/409 , G11C8/18 , G11C11/419 , G11C11/56 , G11C7/10
CPC分类号： G11C11/1693 , G11C7/08 , G11C7/109 , G11C7/22 , G11C7/222 , G11C8/16 , G11C8/18 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C11/4076 , G11C11/419 , G11C11/5607 , G11C13/0023 , G11C13/004 , G11C13/0061 , G11C13/0069
摘要： A semiconductor memory device is capable of executing a first mode having a first latency and a second mode having a second latency longer than the first latency. The semiconductor memory device includes: a pad unit configured to receive an address and a command from an outside; a first delay circuit configured to delay the address by a time corresponding to the first latency; a second delay circuit including shift registers connected in series and configured to delay the address by a time corresponding to a difference between the first latency and the second latency; and a controller configured to use the first delay circuit and the second delay circuit when executing the second mode.
摘要翻译：半导体存储器件能够执行具有第一等待时间的第一模式和具有比第一等待时间长的第二等待时间的第二模式。半导体存储器件包括：焊盘单元，被配置为从外部接收地址和命令; 第一延迟电路，被配置为将所述地址延迟与所述第一等待时间相对应的时间; 第二延迟电路，包括串联连接的移位寄存器，并配置为将地址延迟与第一等待时间和第二等待时间之间的差对应的时间; 以及控制器，被配置为在执行第二模式时使用第一延迟电路和第二延迟电路。

10. 发明授权

US08882238B2 Coating device 有权
标题翻译：涂装装置
公开(公告)号：US08882238B2
公开(公告)日：2014-11-11
申请号：US12602782
申请日：2008-05-15
申请人： Daiki Minamino , Tadatsugu Okumura , Ichiro Miyagawa , Tomohiko Sakai , Naoki Shimizu , Kiyoshi Akagi
发明人： Daiki Minamino , Tadatsugu Okumura , Ichiro Miyagawa , Tomohiko Sakai , Naoki Shimizu , Kiyoshi Akagi
IPC分类号： B41J2/015 , B41J3/54 , B41J11/00
CPC分类号： B41J3/543 , B41J11/0015 , B41J2202/21
摘要： A coating device is provided with: a plurality of inkjet heads (31) staggered to cover an area to be coated in a width direction of a long-roll supporting body (10); a pressure adjusting mechanism (40) for adjusting the back-pressure of the coating solution to be applied from inkjet heads (31); a plurality of solution feeding pipes (43) for supplying the coating solution from the pressure adjusting mechanism (40) to inkjet heads (31); and storage tank (50) for storing the coating solution, wherein the feeding volumes of the coating solution from the solution feeding pipes (43) are adjusted equal (i.e. flow resistances of the piping are made equal), so that equal back-pressures are applied to the coating solution to be jetted from the inkjet heads.
摘要翻译：一种涂布装置具有：多个喷墨头（31），其交错以覆盖在长辊支撑体（10）的宽度方向上待涂覆的区域; 用于调节从喷墨头（31）施加的涂布溶液的背压的压力调节机构（40）; 多个用于将涂布溶液从压力调节机构（40）供应到喷墨头（31）的溶液供给管（43）; 以及用于储存涂布溶液的储罐（50），其中来自溶液供给管（43）的涂布溶液的进料量被调节为相等（即，使管道的流动阻力相等），使得相等的背压为应用于从喷墨头喷射的涂布溶液。

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