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1. 发明授权

US09613671B2 Nonvolatile random access memory including control circuit configured to receive commands at high and low edges of one clock cycle 有权
公开(公告)号：US09613671B2
公开(公告)日：2017-04-04
申请号：US14692239
申请日：2015-04-21
申请人： Yutaka Shirai , Naoki Shimizu , Kenji Tsuchida , Yoji Watanabe , Ji Hyae Bae , Yong Ho Kim
发明人： Yutaka Shirai , Naoki Shimizu , Kenji Tsuchida , Yoji Watanabe , Ji Hyae Bae , Yong Ho Kim
IPC分类号： G11C8/00 , G11C8/18 , G11C7/12 , G11C8/10 , G11C8/12 , G11C11/16 , G11C7/10
CPC分类号： G11C7/12 , G11C7/1039 , G11C7/222 , G11C8/10 , G11C8/12 , G11C8/18 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C11/1693
摘要： According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.

2. 发明授权

US09530480B2 Semiconductor memory device 有权
公开(公告)号：US09530480B2
公开(公告)日：2016-12-27
申请号：US14864271
申请日：2015-09-24
申请人： Naoki Shimizu , Ji Hyae Bae
发明人： Naoki Shimizu , Ji Hyae Bae
IPC分类号： G11C11/16 , G11C13/00 , G11C7/22 , G11C11/4076 , G11C7/08 , G11C11/409 , G11C11/419 , G11C8/18 , G11C11/56 , G11C7/10 , G11C8/16
CPC分类号： G11C11/1693 , G11C7/08 , G11C7/109 , G11C7/22 , G11C7/222 , G11C8/16 , G11C8/18 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C11/4076 , G11C11/419 , G11C11/5607 , G11C13/0023 , G11C13/004 , G11C13/0061 , G11C13/0069
摘要： A semiconductor memory device is capable of executing a first mode having a first latency and a second mode having a second latency longer than the first latency. The semiconductor memory device includes: a pad unit configured to receive an address and a command from an outside; a first delay circuit configured to delay the address by a time corresponding to the first latency; a second delay circuit including shift registers connected in series and configured to delay the address by a time corresponding to a difference between the first latency and the second latency; and a controller configured to use the first delay circuit and the second delay circuit when executing the second mode.

3. 发明授权

US09171600B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09171600B2
公开(公告)日：2015-10-27
申请号：US14201686
申请日：2014-03-07
申请人： Naoki Shimizu , Ji Hyae Bae
发明人： Naoki Shimizu , Ji Hyae Bae
IPC分类号： G11C11/16 , G11C13/00 , G11C7/22 , G11C11/4076 , G11C7/08 , G11C11/409 , G11C8/18 , G11C11/419 , G11C11/56 , G11C7/10
CPC分类号： G11C11/1693 , G11C7/08 , G11C7/109 , G11C7/22 , G11C7/222 , G11C8/16 , G11C8/18 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C11/4076 , G11C11/419 , G11C11/5607 , G11C13/0023 , G11C13/004 , G11C13/0061 , G11C13/0069
摘要： A semiconductor memory device is capable of executing a first mode having a first latency and a second mode having a second latency longer than the first latency. The semiconductor memory device includes: a pad unit configured to receive an address and a command from an outside; a first delay circuit configured to delay the address by a time corresponding to the first latency; a second delay circuit including shift registers connected in series and configured to delay the address by a time corresponding to a difference between the first latency and the second latency; and a controller configured to use the first delay circuit and the second delay circuit when executing the second mode.
摘要翻译：半导体存储器件能够执行具有第一等待时间的第一模式和具有比第一等待时间长的第二等待时间的第二模式。半导体存储器件包括：焊盘单元，被配置为从外部接收地址和命令; 第一延迟电路，被配置为将所述地址延迟与所述第一等待时间相对应的时间; 第二延迟电路，包括串联连接的移位寄存器，并配置为将地址延迟与第一等待时间和第二等待时间之间的差对应的时间; 以及控制器，被配置为在执行第二模式时使用第一延迟电路和第二延迟电路。

4. 发明授权

US09042198B2 Nonvolatile random access memory 有权
标题翻译：非易失性随机存取存储器
公开(公告)号：US09042198B2
公开(公告)日：2015-05-26
申请号：US14020534
申请日：2013-09-06
申请人： Yutaka Shirai , Naoki Shimizu , Kenji Tsuchida , Yoji Watanabe , Ji Hyae Bae , Yong Ho Kim
发明人： Yutaka Shirai , Naoki Shimizu , Kenji Tsuchida , Yoji Watanabe , Ji Hyae Bae , Yong Ho Kim
IPC分类号： G11C8/00 , G11C7/12 , G11C8/10 , G11C8/12
CPC分类号： G11C7/12 , G11C7/1039 , G11C7/222 , G11C8/10 , G11C8/12 , G11C8/18 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C11/1693
摘要： According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.
摘要翻译：根据一个实施例，存储器包括具有存储体的存储单元阵列，每个存储体包括行，对应于行的第一字线，锁存第一行地址信号的地址锁存电路，第一字线，以及控制电路，被配置为当加载第一命令时，基于存储体地址信号执行第一操作，该第一操作激活存储区中的一个存储体;以及第二操作，其将地址中的第一行地址信号锁存并且执行第三操作，当在第一命令之后加载第二命令时，基于第二行地址信号和锁存在地址锁存电路中的第一行地址信号，由行解码器激活第一字线之一。

5. 发明授权

US09674388B2 Information processing apparatus, information processing system, and information processing method that accept a configuration of a cooperative operation 有权
公开(公告)号：US09674388B2
公开(公告)日：2017-06-06
申请号：US14642935
申请日：2015-03-10
申请人： Tadashi Sato , Hiroyuki Sakuyama , Takayasu Oe , Naoki Shimizu , Genki Umeizumi , Takuya Mori , Junki Aoki
发明人： Tadashi Sato , Hiroyuki Sakuyama , Takayasu Oe , Naoki Shimizu , Genki Umeizumi , Takuya Mori , Junki Aoki
IPC分类号： G06F3/12 , H04N1/00 , G06K15/00
CPC分类号： H04N1/0096 , G06F3/1205 , G06F3/1215 , G06F3/1253 , G06F3/1275 , G06F3/1285 , H04N2201/0094
摘要： An information processing apparatus includes an acceptance unit that accepts a configuration of a cooperative operation to be performed by multiple apparatuses cooperating with each other, an execution order determination unit that determines an executing order of processes included in the cooperative operation, an apparatus determination unit that identifies, for each of the processes included in the cooperative operation, an apparatus that performs the process, and a controller that instructs the identified apparatus to execute the processes included in the cooperative operation in the determined executing order.

6. 发明授权

US09184743B2 Control apparatus for switching device 有权
标题翻译：开关装置用控制装置
公开(公告)号：US09184743B2
公开(公告)日：2015-11-10
申请号：US13612664
申请日：2012-09-12
申请人： Naoki Shimizu
发明人： Naoki Shimizu
IPC分类号： H02H3/08 , H03K17/567 , H03K17/082
CPC分类号： H03K17/567 , H03K17/082
摘要： A control apparatus for a switching device which suppresses surge voltages at the time of current shutoff of a switching device to protect from overcurrents although the switching device is not in an overcurrent state, including a current sensor, a comparator, a timer latch, a control circuit, and a transistor. The current sensor detects the current of a switching device and outputs a detected voltage. The comparator outputs a signal when the detected voltage is equal to or greater than a reference voltage. When the time duration of the output signal is equal to or greater than a setting time, the timer latch outputs a surge suppression detection signal, based on which the control circuit outputs to the transistor a driving signal to turn off the switching device. The reference voltage is smaller than a reference voltage used when detecting an overcurrent flowing in the switching device.
摘要翻译：一种用于开关装置的控制装置，其抑制开关装置的电流切断时的浪涌电压，以防止开关器件不处于过电流状态，包括电流传感器，比较器，定时器锁存器，控制器电路和晶体管。电流传感器检测开关器件的电流并输出检测到的电压。当检测电压等于或大于参考电压时，比较器输出信号。当输出信号的持续时间等于或大于设定时间时，定时器锁存器输出浪涌抑制检测信号，基于该脉冲抑制检测信号，控制电路向晶体管输出驱动信号以关闭开关器件。参考电压小于检测在开关装置中流过的过电流时使用的基准电压。

7. 发明授权

US09035984B2 Printing system and printing apparatus 有权
标题翻译：印刷系统和印刷设备
公开(公告)号：US09035984B2
公开(公告)日：2015-05-19
申请号：US14446713
申请日：2014-07-30
申请人： Yuichi Aihara , Naoki Shimizu , Tomohisa Koike
发明人： Yuichi Aihara , Naoki Shimizu , Tomohisa Koike
IPC分类号： G01D15/16 , B41J2/325
CPC分类号： B41J2/325
摘要： A printing system and printing apparatus are provided with improvements in the image quality of an image formed on a printing medium, a peel off region (PO) wherein a transfer layer of a transfer film is not transferred is set corresponding to a card, modified printing data is generated by modifying a gray-scale value of printing data inside a region that is larger than the PO region by predetermined dimensions and including the PO region in the printing data of Y, M, C and Bk into a gray-scale value of 0, an image is formed on the transfer film by heating a thermal head for an image formation panel of an ink ribbon according to the modified printing data. The transfer layer is peeled off by heating the thermal head for a peel off panel of the ink ribbon according to position information of the PO region.
摘要翻译：提供一种打印系统和打印设备，其对打印介质上形成的图像的图像质量进行改进，对应于卡设置转印膜的未转印转印层的剥离区域（PO），修改印刷通过将大于PO区域的区域内的打印数据的灰度值修改为预定尺寸并且将Y，M，C和Bk的打印数据中的PO区域包括在灰度值的灰度值中来生成数据 0，通过根据修改的打印数据加热色带的图像形成面板的热敏头来在转印膜上形成图像。根据PO区域的位置信息，通过加热墨带的剥离板的热敏头来剥离转印层。

8. 发明授权

US07859821B2 Multilayer ceramic electronic component 有权
标题翻译：多层陶瓷电子元件
公开(公告)号：US07859821B2
公开(公告)日：2010-12-28
申请号：US12784553
申请日：2010-05-21
申请人： Naoki Shimizu
发明人： Naoki Shimizu
IPC分类号： H01G4/228 , H01G4/005 , H01G4/06
CPC分类号： H01G4/30 , H01G4/012 , H01G4/12
摘要： A multilayer ceramic capacitor includes first internal electrodes extending to a first end surface of a ceramic element assembly, a plurality of second internal electrodes extending to a second end surface, floating internal electrodes arranged so as to overlap the first and second internal electrodes with ceramic layers disposed therebetween to define first and second effective regions, inner conductors that are elongated from the first end surface beyond a region that overlaps the first effective region in the direction of layering, and a relationship X1
摘要翻译：多层陶瓷电容器包括延伸到陶瓷元件组件的第一端面的第一内部电极，延伸到第二端面的多个第二内部电极，布置成与第一和第二内部电极重叠的陶瓷层的浮动内部电极设置在它们之间以限定第一和第二有效区域，内部导体从第一端面延伸超过在分层方向上与第一有效区域重叠的区域，并且满足X1

9. 发明授权

US07208915B2 Constant-current battery charger 有权
标题翻译：恒流电池充电器
公开(公告)号：US07208915B2
公开(公告)日：2007-04-24
申请号：US11237786
申请日：2005-09-29
申请人： Atsumasa Kubota , Tatsuya Miwa , Masaki Ikeda , Naoki Shimizu
发明人： Atsumasa Kubota , Tatsuya Miwa , Masaki Ikeda , Naoki Shimizu
IPC分类号： H02J7/00
CPC分类号： H02J7/0072 , H02J7/06
摘要： A constant-current battery charger includes a power supply for supplying a charge current to a secondary cell, and a current monitor for monitoring a charge current being supplied to the cell. A controller is included for varying the charge current in accordance with the monitored charge current. The controller calculates a current difference between a predetermined target current and the instant charge current, and generates a demand of varying the charge current at a first charge rate when the current difference is out of a predetermined range, and varying the charge current at a second charge rate when the current difference is within the predetermined range. The controller generates the demand repeatedly at regular or varying intervals for varying the charge current. The first charge rate is set to be higher than the second charge rate in order to make a rapid charging until it comes close to the target current. Since the current difference between the instant charge current and the target current is relied upon to switch the charge rate between the first and second charge rates, the switching can be made at an exact timing truly indicative of the condition of the battery, which enables a rapid charging, yet assuring to complete the charging successfully.
摘要翻译：恒流电池充电器包括用于向二次电池提供充电电流的电源，以及用于监视被提供给电池的充电电流的电流监视器。包括用于根据监视的充电电流来改变充电电流的控制器。控制器计算预定目标电流和瞬时充电电流之间的电流差，并且当电流差超出预定范围时产生以第一充电速率改变充电电流的需求，并且在第二充电电流下改变充电电流当电流差在预定范围内时的充电率。控制器以规则或变化的间隔重复地产生需求以改变充电电流。第一充电速率被设置为高于第二充电速率，以便在接近目标电流之前进行快速充电。由于瞬时充电电流和目标电流之间的电流差异依赖于在第一和第二充电速率之间切换充电速率，所以可以在真实地指示电池状态的确切时间进行切换，这使得能够快速充电，但确保成功完成充电。

10. 发明授权

US6053643A Solid processing agent storing container for photosensitive material processing 失效
标题翻译：固体处理剂储存容器用于感光材料加工
公开(公告)号：US6053643A
公开(公告)日：2000-04-25
申请号：US241815
申请日：1999-02-01
申请人： Kiyokazu Tanahashi , Nobuaki Takahashi , Toshio Kato , Michihide Murase , Hideo Kobayashi , Naoki Shimizu , Osamu Shibazaki , Tomohiro Uchida , Masahiko Taguchi
发明人： Kiyokazu Tanahashi , Nobuaki Takahashi , Toshio Kato , Michihide Murase , Hideo Kobayashi , Naoki Shimizu , Osamu Shibazaki , Tomohiro Uchida , Masahiko Taguchi
IPC分类号： G03D3/06 , G03D3/02
CPC分类号： G03D3/065
摘要： In a container for storing plural different kinds of photosensitive material processing agents provided with a first storing room having a first opening; a second storing room having a second opening; a third storing room having a third opening; a first flange section to enclose the periphery of the first opening; a second flange section to enclose the periphery of both the second opening and the third opening; and a cover member to cover the first opening, the second opening and the third opening, the second storing room is located between the first storing room and the third storing room and a first distance between the first storing room and the second storing room and is made larger than a second distance between the second storing room and the third storing room.
摘要翻译：在用于存储多种不同种类的感光材料处理剂的容器中，所述感光材料处理剂设置有具有第一开口的第一存储室; 具有第二开口的第二存储室; 具有第三开口的第三储存室; 第一凸缘部，其包围第一开口的周边; 第二凸缘部，其包围第二开口和第三开口的周边; 以及覆盖所述第一开口，所述第二开口和所述第三开口的盖构件，所述第二存储室位于所述第一存储室和所述第三存储室之间，并且位于所述第一存储室和所述第二存储室之间的第一距离，并且是在第二存储室和第三存储室之间大于第二距离。

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