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1. 发明申请

WO2011059639A3 DAMASCENE GATE HAVING PROTECTED SHORTING REGIONS 审中-公开
标题翻译：具有受保护的小区的DAMASCENE GATE
公开(公告)号：WO2011059639A3
公开(公告)日：2011-07-28
申请号：PCT/US2010053091
申请日：2010-10-19
申请人： IBM , ANDERSON BRENT A , NOWAK EDWARD J , RANKIN JED H
发明人： ANDERSON BRENT A , NOWAK EDWARD J , RANKIN JED H
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/28247 , H01L21/76834 , H01L21/76897
摘要： The present invention relates generally to semiconductor devices and, more specifically, to damascene gates (100; Fig 1C) having protected shorting regions (60) and related methods for their manufacture. A first aspect of the invention provides a method of forming a damascene gate (100) with protected shorting regions (60), the method comprising: forming a damascene gate having: a gate dielectric atop a substrate (12); a gate conductor (40) atop the gate dielectric; a conductive liner laterally adjacent the gate conductor (30); a spacer between the conductive liner and the substrate (20); and a first dielectric atop the gate conductor (60); removing a portion of the conductive liner (30); and depositing a second dielectric (60) atop a remaining portion of the conductive liner (30), such that the second dielectric is laterally adjacent both the first dielectric and the gate.
摘要翻译：本发明一般涉及半导体器件，并且更具体地涉及具有受保护的短路区域（60）的镶嵌栅极（100;图1C）以及用于其制造的相关方法。本发明的第一方面提供一种形成具有受保护的短路区域（60）的镶嵌栅极（100）的方法，所述方法包括：形成镶嵌栅极，所述镶嵌栅极具有：衬底（12）顶上的栅极电介质; 在所述栅极电介质顶上的栅极导体（40）横向邻近栅极导体（30）的导电衬垫; 导电衬垫和衬底（20）之间的间隔件; 以及在所述栅极导体（60）顶上的第一电介质; 去除导电衬里（30）的一部分; 以及在所述导电衬垫（30）的剩余部分顶上沉积第二电介质（60），使得所述第二电介质横向邻近所述第一电介质和所述栅极。

2. 发明申请

WO2010138278A3 INTEGRATED CIRCUIT DEVICE WITH DEEP TRENCH ISOLATION REGIONS FOR ALL INTER-WELL AND INTRA-WELL ISOLATION AND WITH A SHARED CONTACT TO A JUNCTION BETWEEN ADJACENT DEVICE DIFFUSION REGIONS AND AN UNDERLYING FLOATING WELL SECTION 审中-公开
标题翻译：具有深度分离隔离区域的集成电路设备，用于所有内部和内部隔离以及与共享设备扩展区域和下面的浮动区段之间的连接的共享接触
公开(公告)号：WO2010138278A3
公开(公告)日：2011-02-03
申请号：PCT/US2010033469
申请日：2010-05-04
申请人： IBM , ANDERSON BRENT A , BRYANT ANDRES , NOWAK EDWARD J
发明人： ANDERSON BRENT A , BRYANT ANDRES , NOWAK EDWARD J
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L27/0207 , H01L21/823481 , H01L21/823493 , H01L27/092 , H01L27/11 , H01L27/1104
摘要： Disclosed are embodiments of an improved integrated circuit device structure (200) (e.g., a static random access memory array structure or other integrated circuit device structure incorporating both P-type and N-type devices) (121a and 121b) and a method of forming the structure that uses DTI regions (160) for all inter- well and intra- well isolation and, thereby provides a low-cost isolation scheme that avoids FET width variations due to STI-DTI misalignment. Furthermore, because the DTI regions (160) used for intra- well isolation effectively create some floating well sections, (203) which must each be connected to a supply voltage (e.g., Vdd) (280) to prevent threshold voltage (Vt) variations, the disclosed integrated circuit device also includes a shared contact (280) to a junction between the diffusion regions (221 and 222) of adjacent devices (121a and 121b) and an underlying floating well section (205). This shared contact (280) eliminates the cost and area penalties that would be incurred if a discrete supply voltage contact was required for each floating well section (205).
摘要翻译：公开了改进的集成电路器件结构（200）（例如，并入P型和N型器件的静态随机存取存储器阵列结构或其他集成电路器件结构）（121a和121b）的实施例和形成方法使用DTI区域（160）进行所有井间和井内隔离的结构，从而提供了一种低成本隔离方案，可避免由于STI-DTI失准导致的FET宽度变化。此外，由于用于井内隔离的DTI区域（160）有效地产生一些浮动井区段（203），其必须各自连接到电源电压（例如Vdd）（280），以防止阈值电压（Vt）变化所公开的集成电路器件还包括到相邻器件（121a和121b）的扩散区域（221和222）与下面的浮动阱区段（205）之间的连接处的共用触点（280）。这种共享联系人（280）消除了如果每个浮动井段（205）需要离散的电源电压接触，将会产生的成本和面积的惩罚。

3. 发明申请

WO2010126768A1 THRESHOLD VOLTAGE ADJUSTMENT THROUGH GATE DIELECTRIC STACK MODIFICATION 审中-公开
标题翻译：通过门电介质堆栈修正进行阈值电压调节
公开(公告)号：WO2010126768A1
公开(公告)日：2010-11-04
申请号：PCT/US2010/031998
申请日：2010-04-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GREENE, Brian, J. , CHUDZIK, Michael, P. , HAN, Shu-jen , HENSON, William, K. , LIANG, Yue , MACIEJEWSKI, Edward, P. , NA, Myung-hee , NOWAK, Edward, J. , YU, Xiaojun
发明人： GREENE, Brian, J. , CHUDZIK, Michael, P. , HAN, Shu-jen , HENSON, William, K. , LIANG, Yue , MACIEJEWSKI, Edward, P. , NA, Myung-hee , NOWAK, Edward, J. , YU, Xiaojun
IPC分类号： H01L21/283 , H01L29/49
CPC分类号： H01L21/823462 , H01L21/28229 , H01L21/84 , H01L27/1203
摘要： Multiple types of gate stacks (100,..., 600) are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric (30L) is formed on the doped semiconductor well (22, 24). A metal gate layer (42L) is formed in one device area, while the high-k gate dielectric is exposed in other device areas (200, 400, 500, 600). Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer (72L) is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.
摘要翻译：在掺杂半导体阱上形成多种类型的栅叠层（100，...，600）。在掺杂半导体阱（22,24）上形成高介电常数（高k）栅极电介质（30L）。金属栅极层（42L）形成在一个器件区域中，而高k栅极电介质暴露在其他器件区域（200,400,500,600）中。在其他器件区域中形成具有不同厚度的阈值电压调节氧化物层。然后在阈值电压调整氧化物层上形成导电栅极材料层（72L）。一种类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质。其他类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质和具有不同厚度的第一阈值电压调整氧化物部分。具有不同阈值电压的场效应晶体管通过采用具有相同掺杂剂浓度的不同栅极电介质叠层和掺杂半导体阱来提供。

4. 发明申请

WO2010008748A8 SPACER FILL STRUCTURE, METHOD AND DESIGN STRUCTURE FOR REDUCING DEVICE VARIATION 审中-公开
标题翻译：隔膜填充结构，减少设备变化的方法和设计结构
公开(公告)号：WO2010008748A8
公开(公告)日：2010-04-22
申请号：PCT/US2009047719
申请日：2009-06-18
申请人： IBM , ANDERSON BRENT A , BRYANT ANDRES , NOWAK EDWARD J , RANKIN JED H
发明人： ANDERSON BRENT A , BRYANT ANDRES , NOWAK EDWARD J , RANKIN JED H
IPC分类号： H01L21/334
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A design structure (100, FIG. 1a) is provided for spacer fill structures (100 and 300) and, more particularly, spacer fill structures (100 and 300), a method of manufacturing and a design structure for reducing device variation is provided. The structure includes a plurality of dummy fill shapes (100) in different areas of a device which are configured such that gate perimeter to gate area ratio will result in a total perimeter density being uniform across a chip.
摘要翻译：提供了用于间隔物填充结构（100和300）的设计结构（100，图1a），更具体地，提供了间隔件填充结构（100和300），制造方法和用于减小装置变化的设计结构。该结构包括在器件的不同区域中的多个虚拟填充形状（100），其被配置为使得栅极周边与栅极面积比将导致整个芯片的总周边密度是均匀的。

5. 发明申请

WO2010018070A1 METAL-GATE HIGH-K REFERENCE STRUCTURE 审中-公开
标题翻译：金属高K参考结构
公开(公告)号：WO2010018070A1
公开(公告)日：2010-02-18
申请号：PCT/EP2009/059880
申请日：2009-07-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , NOWAK, Edward , ANDERSON, Brent, Alan
发明人： NOWAK, Edward , ANDERSON, Brent, Alan
IPC分类号： H01L21/8234 , H01L29/49 , H01L29/51 , H01L27/088
CPC分类号： H01L21/823462 , H01L21/82345 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/785
摘要： Disclosed are embodiments of an integrated circuit structure that incorporates at least two field effect transistors (FETs) that have the same conductivity type and essentially identical semiconductor bodies (i.e., the same semiconductor material and, thereby the same conduction and valence band energies, the same source, drain, and channel dopant profiles, the same channel widths and lengths, etc.). However, due to different gate structures with different effective work functions, at least one of which is between the conduction and valence band energies of the semiconductor bodies, these FETs have selectively different threshold voltages, which are independent of process variables. Furthermore, through the use of different high-k dielectric materials and/or metal gate conductor materials, the embodiments allow threshold voltage differences of less than 700mV to be achieved so that the integrated circuit structure can function at power supply voltages below 1.0V. Also disclosed are method embodiments for forming the integrated circuit structure.
摘要翻译：公开了集成电路结构的实施例，该集成电路结构包含至少两个场效应晶体管（FET），其具有相同的导电类型和基本相同的半导体主体（即，相同的半导体材料，并且因此相同的导通和价带能量相同源极，漏极和沟道掺杂物分布，相同的沟道宽度和长度等）。然而，由于具有不同的具有不同有效功函数的栅极结构，其中至少一个位于半导体本体的导通能量和价带能量之间，所以这些FET具有不同于过程变量的选择性不同的阈值电压。此外，通过使用不同的高k电介质材料和/或金属栅导体材料，实施例允许实现小于700mV的阈值电压差，使得集成电路结构可以在低于1.0V的电源电压下起作用。还公开了用于形成集成电路结构的方法实施例。

6. 发明申请

WO2010008748A1 SPACER FILL STRUCTURE, METHOD AND DESIGN STRUCTURE FOR REDUCING DEVICE VARIATION 审中-公开
标题翻译：用于减小装置变化的间隔件填充结构，方法和设计结构
公开(公告)号：WO2010008748A1
公开(公告)日：2010-01-21
申请号：PCT/US2009/047719
申请日：2009-06-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ANDERSON, Brent, A. , BRYANT, Andres , RANKIN, Jed, H. , NOWAK, Edward, J.
发明人： ANDERSON, Brent, A. , BRYANT, Andres , RANKIN, Jed, H. , NOWAK, Edward, J.
IPC分类号： H01L21/334
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A design structure (100, FIG. 1a) is provided for spacer fill structures (100 and 300) and, more particularly, spacer fill structures (100 and 300), a method of manufacturing and a design structure for reducing device variation is provided. The structure includes a plurality of dummy fill shapes (100) in different areas of a device which are configured such that gate perimeter to gate area ratio will result in a total perimeter density being uniform across a chip.
摘要翻译：提供用于间隔件填充结构（100和300）的设计结构（100，图1a），并且更具体地提供间隔件填充结构（100和300），制造方法和设计提供了用于减小设备变化的结构。该结构包括在器件的不同区域中的多个虚拟填充形状（100），其被配置为使得栅极周边与栅极面积之比将导致整个芯片上的总周边密度是均匀的。

7. 发明申请

WO2007011496A3 HIGH PERFORMANCE CAPACITORS IN PLANAR BACK GATES CMOS 审中-公开
标题翻译：高性能电容器在平面背栅CMOS
公开(公告)号：WO2007011496A3
公开(公告)日：2008-05-29
申请号：PCT/US2006024701
申请日：2006-06-26
申请人： IBM , BRYANT ANDRES , NOWAK EDWARD J , WILLIAMS RICHARD Q
发明人： BRYANT ANDRES , NOWAK EDWARD J , WILLIAMS RICHARD Q
IPC分类号： H01L21/84 , H01L27/108
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0811 , H01L28/40 , H01L29/78648 , Y10T436/235 , Y10T436/25125 , Y10T436/2525 , Y10T436/25375
摘要： A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate (106a-d) in an insulating layer (100) and a second plate (110a-d) above the insulating layer electrically corresponding to the first plate. An isolation structure (108a-d) is between the first plate and the second plate.
摘要翻译：一种双栅极CMOS结构的制造方法和器件。该结构包括绝缘层（100）中的第一板（106a-d）和与第一板电对应的绝缘层上方的第二板（110a-d）。隔离结构（108a-d）位于第一板和第二板之间。

8. 发明申请

WO2007082266A3 SEMICONDUCTOR TRANSISTORS WITH EXPANDED TOP PORTIONS OF GATES 审中-公开
标题翻译：半导体晶体管，带有扩大的顶部分
公开(公告)号：WO2007082266A3
公开(公告)日：2007-12-06
申请号：PCT/US2007060390
申请日：2007-01-11
申请人： IBM , ANDERSON BRENT A , CHAN VICTOR W C , NOWAK EDWARD J
发明人： ANDERSON BRENT A , CHAN VICTOR W C , NOWAK EDWARD J
IPC分类号： H01L21/76
CPC分类号： H01L29/66477 , H01L21/26506 , H01L21/28052 , H01L21/28114 , H01L21/28518 , H01L29/1083 , H01L29/42376 , H01L29/66507 , H01L29/6659 , H01L29/66772 , H01L29/66795 , H01L29/785 , H01L29/78654
摘要： A semiconductor transistor (100) with an expanded top portion of a gate and a method for forming the same. The semiconductor transistor (100) with an expanded top portion of a gate includes (a) a semiconductor region (110)which includes a channel region and first and second source/drain regions (840 and 850); the channel region is disposed between the first and second source/drain regions (840 and 850), (b) a gate dielectric region (411) in direct physical contact with the channel region, and (c) a gate electrode region (510) which includes a top portion (512) and a bottom portion (515). The bottom portion (515) is in direct physical contact with the gate dielectric region (411). A first width (517) of the top portion (512) is greater than a second width (516) of the bottom portion (515). The gate electrode region (510) is electrically insulated from the channel region by the gate dielectric region (411).
摘要翻译：一种具有扩大的栅极顶部的半导体晶体管（100）及其形成方法。具有扩展的栅极顶部部分的半导体晶体管（100）包括：（a）包括沟道区以及第一和第二源极/漏极区（840和850）的半导体区（110）; 沟道区设置在第一和第二源极/漏极区（840和850）之间，（b）与沟道区直接物理接触的栅极介电区（411），以及（c）栅电极区（510）其包括顶部（512）和底部（515）。底部（515）与栅极电介质区域（411）直接物理接触。顶部（512）的第一宽度（517）大于底部（515）的第二宽度（516）。栅极电极区域（510）通过栅极电介质区域（411）与沟道区域电绝缘。

9. 发明申请

WO2007019023A2 FIN-TYPE FIELD EFFECT TRANSISTOR 审中-公开
标题翻译： FIN型场效应晶体管
公开(公告)号：WO2007019023A2
公开(公告)日：2007-02-15
申请号：PCT/US2006/028465
申请日：2006-07-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , NOWAK, Edward, J.
发明人： NOWAK, Edward, J.
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/7856
摘要： Disclosed herein are improved fin-type field effect transistor (FinFET) structures (100) and the associated methods of manufacturing the structures. In one embodiment FinFET drive current is optimized by configuring the FinFET (100) asymmetrically to decrease fin resistance between the gate (120) and the source region (101 ) and to decrease capacitance between the gate (120) and the drain region (102). In another embodiment device destruction at high voltages is prevented by ballasting the FinFET (300). Specifically, resistance is optimized in the fin (350) between the gate (320) and both the source (301 ) and drain (302) regions (e.g., by increasing fin length (383), by blocking source/drain implant from the fin (350), and by blocking silicide formation on the top surface (395) of the fin) so that the FinFET (300) is operable at a predetermined maximum voltage.
摘要翻译：本文公开了改进的鳍式场效应晶体管（FinFET）结构（100）以及相关的制造结构的方法。在一个实施例中，通过非对称地配置FinFET（100）来降低栅极（120）和源极区域（101）之间的鳍电阻并降低栅极（120）和漏极区域（102）之间的电容来优化FinFET驱动电流，。在另一实施例中，通过对FinFET（300）进行镇流来防止在高电压下的破坏。具体来说，在栅极（320）和源极（301）和漏极（302）区域之间的鳍片（350）中电阻被优化（例如，通过增加鳍片长度（383），通过从鳍片阻挡源极/漏极注入（350），并且通过阻挡在鳍的顶表面（395）上的硅化物形成，使得FinFET（300）可在预定的最大电压下操作。

10. 发明申请

WO2006122096A2 METHOD AND STRUCTURES FOR MEASURING GATE TUNNELING LEAKAGE PARAMETERS OF FIELD EFFECT TRANSISTORS 审中-公开
标题翻译：用于测量场效应晶体管的栅极隧道漏电参数的方法和结构
公开(公告)号：WO2006122096A2
公开(公告)日：2006-11-16
申请号：PCT/US2006017863
申请日：2006-05-09
申请人： IBM , NOWAK EDWARD J , NA MYUNG-HE
发明人： NOWAK EDWARD J , NA MYUNG-HE
IPC分类号： G01R31/26
CPC分类号： H01L22/34 , H01L29/42384 , H01L29/78609 , H01L29/78615
摘要： A structure (100) and method for measuring leakage current. The structure includes: a body (105) formed in a semiconductor substrate (175); a dielectric layer (125/130) on a top surface of the silicon body (105); and a conductive layer (110) on a top surface of the dielectric layer (125/130), a first region of the dielectric layer (125/130) having a first thickness (T1) and a second region of the dielectric layer (125/130) between the conductive layer (110)and the top surface of the body (105) having a second thickness (T2), the second thickness (T2) different from the first thickness (T1). The method includes, providing two of the above structures (100) having different areas of first and the same area of second or having different areas of second and the same area of first dielectric regions (125/130), measuring a current between the conductive layer (110) and the body (105) for each structure (100) and calculating a gate tunneling leakage current based on the current measurements and dielectric layer (125/130) areas of the two devices.
摘要翻译：一种用于测量漏电流的结构（100）和方法。该结构包括：形成在半导体衬底（175）中的主体（105）; 在硅体（105）的顶表面上的介电层（125/130）; 和介电层（125/130）的顶表面上的导电层（110），具有第一厚度（T1）和电介质层（125）的第二区域的电介质层（125/130）的第一区域导电层（110）和具有第二厚度（T2）的本体（105）的顶表面之间，第二厚度（T2）与第一厚度（T1）不同。该方法包括：提供两个上述结构（100），其具有第一和相同面积区域的不同区域，或具有第二和相同面积的第一介电区域（125/130）的不同区域，测量导电（100）的层（110）和主体（105），并且基于两个器件的电流测量和电介质层（125/130）区域计算栅极隧道漏电流。

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