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1. 发明专利

JP2006125829A Monitoring method for furnace apparatus 审中-公开
标题翻译：火炉设备监控方法
公开(公告)号：JP2006125829A
公开(公告)日：2006-05-18
申请号：JP2005176487
申请日：2005-06-16
申请人： Mosel Vitelic Inc , モーゼルヴィテリックインコーポレイテッド
发明人： CHIU MING-HUNG , SUN PEI-FENG , PAN KUO-PIN , WU SHENG-LUNG
IPC分类号： F27D21/00 , C21D11/00 , F27B17/00 , F27D11/02 , F27D19/00 , F27D21/04 , H01L21/00 , H01L21/02
CPC分类号： F27B17/0025 , C21D11/00 , F27D19/00 , F27D21/0014 , F27D21/04 , H01L21/67109 , H01L21/67248
摘要： PROBLEM TO BE SOLVED: To provide a method for monitoring a furnace apparatus without needing stoppage of the furnace apparatus or waiting up to a PM (preventive maintenance) cycle while releasing an employee from a temperature rise rate during operation of the furnace apparatus.
SOLUTION: The monitoring method includes powering on the furnace apparatus to a specific power value; recording the temperature rise rate of the furnace apparatus; and comparing the temperature rise rate with a predetermined threshold value, wherein the furnace apparatus is replaced when the rise rate is under the threshold value.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于在炉膛操作期间释放员工免受升温速率而不需要停止炉装置或等待PM（预防性维护）循环的炉设备的监控方法。
解决方案：监测方法包括将炉装置上电到特定功率值; 记录炉装置的升温速度; 以及将所述升温速率与预定阈值进行比较，其中当所述上升速率低于所述阈值时更换所述炉设备。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2005101497A Development method 有权
标题翻译：发展方式
公开(公告)号：JP2005101497A
公开(公告)日：2005-04-14
申请号：JP2004032897
申请日：2004-02-10
申请人： Mosel Vitelic Inc , モーゼルヴィテリックインコーポレイテッド
发明人： LIN CHEN TANG , YEH CHUNG CHIH , PENG KO WEI , WU MING FENG
IPC分类号： G03F7/30 , G03B27/42 , G03D5/00 , H01L21/02 , H01L21/027
CPC分类号： G03D5/00
摘要： PROBLEM TO BE SOLVED: To effectively prevent a developer solution from remaining on a wafer while avoiding the defects related to conventional technologies.
SOLUTION: A wafer provided with an exposure photoresist is arranged in a reactive space provided for a developing process. The surface of wafer is coated with a developer solution, and the wafer is rotated. The upper and lower surfaces of the wafer are cleaned, and cleaning of the upper surface of the wafer is stopped for a specified period while the lower surface is continued to be cleaned. The wafer provided with the exposure photoresist is disposed on the chuck of a coating equipment, and the surface of wafer is coated with the developer solution. The wafer is rotated to degas the coating equipment so that a water wall is formed between the wafer and the outer wall of a groove. The upper and lower surfaces of the wafer are cleaned by a nozzle, and cleaning of the upper surface of the wafer is stopped for a specified period while cleaning of the lower surface is continued, thus the contamination remaining on the lower surface of the wafer is removed.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：有效地防止显影剂溶液残留在晶片上，同时避免与常规技术相关的缺陷。解决方案：设置有曝光光刻胶的晶片布置在为显影过程提供的反应空间中。用显影剂溶液涂覆晶片的表面，并旋转晶片。清洁晶片的上表面和下表面，并且在继续清洁下表面的同时，将晶片的上表面的清洁停止指定的时间。设置有曝光光致抗蚀剂的晶片设置在涂布设备的卡盘上，并且用显影剂溶液涂覆晶片的表面。旋转晶片以使涂层设备脱气，从而在晶片和凹槽的外壁之间形成水壁。晶片的上表面和下表面通过喷嘴清洁，并且在继续清洁下表面的同时清洁晶片的上表面达指定时间，因此残留在晶片下表面上的污染物为除去。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2005051244A Method for manufacturing integrated circuit 审中-公开
标题翻译：制造集成电路的方法
公开(公告)号：JP2005051244A
公开(公告)日：2005-02-24
申请号：JP2004221666
申请日：2004-07-29
申请人： Mosel Vitelic Inc , モーゼルヴィテリックインコーポレイテッド
发明人： DING YI
IPC分类号： H01L27/10 , H01L21/82 , H01L21/8239 , H01L21/8247 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a novel method for manufacturing an integrated circuit, having a non-volatile memory cell having a first conductive gate, a second conductive gate, and a conductive floating gate isolated from one another.
SOLUTION: A first conductive gate is formed on a semiconductor base layer; a dielectric is formed on the sidewall of the first conductive gate to isolate the gate from a floating gate; a floating gate layer which has a part of the floating gate is formed on the first conductive gate; the floating gate layer is removed from at least part of the first conductive gate; a second conductive gate layer is formed on the floating gate layer to give at least part of the second conductive gate having a protruding portion on the first conductive gate; a layer L1 is formed on the second conductive gate layer in such a way that the protruding portion is exposed and the second conductive gate layer is not covered completely by the layer L1; the second conductive gate layer is partially removed selectively at a portion P1 for the layer L1 and thus the second conductive gate layer is removed from at least part of the first conductive gate, a layer L2 is formed on the second conductive gate layer near the first conductive gate, and the second conductive gate layer and the floating gate layer are removed at least partially with respect to the layer L2.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于制造集成电路的新颖方法，其具有具有彼此隔离的第一导电栅极，第二导电栅极和导电浮栅的非易失性存储单元。解决方案：第一导电栅极形成在半导体基底层上; 电介质形成在第一导电栅极的侧壁上以将栅极与浮动栅极隔离; 在第一导电栅极上形成具有浮置栅极的一部分的浮栅层; 从第一导电栅极的至少一部分去除浮栅层; 在所述浮栅上形成第二导电栅极层，以使所述第二导电栅极的至少一部分在所述第一导电栅极上具有突出部分; 在第二导电栅极层上形成层L1，使得突出部分露出，并且第二导电栅极层未被层L1完全覆盖; 在层L1的部分P1处选择性地部分地去除第二导电栅极层，因此从第一导电栅极的至少一部分去除第二导电栅极层，在靠近第一导电栅极的第二导电栅极层上形成层L2 导电栅极，并且至少部分地相对于层L2去除第二导电栅极层和浮置栅极层。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2001291653A METHOD AND DEVICE FOR IMPROVING EXPOSURE RESOLVING POWER OF EXPOSURE STEPPER 失效
公开(公告)号：JP2001291653A
公开(公告)日：2001-10-19
申请号：JP2000105287
申请日：2000-04-06
申请人： PROMOS TECHNOLOGIES INC , MOSEL VITELIC INC , SIEMENS AG
发明人： CHIN-TE IE , WALTER TON
IPC分类号： G03F7/22 , H01L21/027
摘要： PROBLEM TO BE SOLVED: To provide a method and a device for improving the exposure resolving power of an exposure stepper, where a binary mask is used and the advantage of a phase shift mask is given, and an inconvenient problem due to the usage of the phase mask can be solved. SOLUTION: In an optical system of a general exposure stepper, a one phase shift filter is given to the rear focused surface of a first projection lens, or a shifter and an attenuator are given respectively thereto, thereby making the edge to be vertical in the distribution of intensity of transmitting light and improving the image formation resolving power for a silicon wafer.

5. 发明专利

JP2001085431A BPSG PLANARIZING METHOD WITH IMPROVED PLANARITY WITHOUT ANY CHATTER MARK DEFECTS 失效
公开(公告)号：JP2001085431A
公开(公告)日：2001-03-30
申请号：JP24745299
申请日：1999-09-01
申请人： PROMOS TECHNOLOGIES INC , MOSEL VITELIC INC , SIEMENS AG
发明人： DEN EINEN
IPC分类号： H01L21/3205 , H01L21/306 , H01L21/316
摘要： PROBLEM TO BE SOLVED: To improve flatness of a BPSG layer by forming a second BPSG layer on a first BPSG layer, and reflowing the second BPSG layer in a thermal processing. SOLUTION: A first BPSG(borophosphosilicate glas) layer 101 comprises 3-5% of boron dopant level and 4-5% of phosphorus dopant level and is deposited on a lower layer structure for about 30 minutes. On the first BPSG layer 101, a second BPSG layer 201 is formed using LPCVD with tetraethylorthosilicate as a reactive gas. The second BPSG layer 201 comprises 4-7% of boron dopant level and 1-4% of phosphorus dopant level and is reflowed in a thermal process. Thus, the second BPSG layer 201 is planarized.

6. 发明专利

JP2000075491A Method for decreasing influence of reflection in execution process of photolithography method 有权
标题翻译：降低光刻方法执行反射影响的方法
公开(公告)号：JP2000075491A
公开(公告)日：2000-03-14
申请号：JP24504998
申请日：1998-08-31
申请人： Mosel Vitelic Inc , Promos Technol Inc , Siemens Ag , シーメンス・アクチェンゲゼルシャフト , プロモス.テクノロジイズ.インコーポレイテッド , モーゼル.ヴァイテリック.インコーポレイテッド
发明人： WEN-PIN EN , CHIA-RIN KUU
IPC分类号： G03F7/11 , G03F7/09 , H01L21/027
CPC分类号： H01L21/0276 , G03F7/091
摘要： PROBLEM TO BE SOLVED: To prevent the occurrence of a problem associated with undesirable reflection by effectively controlling the intensity of the reflected ray to be encountered in the execution process of a photolithography method by using a guide material antireflection coating (DARC) layer. SOLUTION: The DARC layer 32 is formed by plasma CVD using SiH4 and H2O deposited by evaporation on a primer coating layer 31 as reactetants. The DARC layer 32 is composed of an SixOyNz material. If the compsn. of the DARC layer 32 is achieved by changing the amts. of the material compsn. (x, y, z) by regulation of the flow rate and processing time of reactive gases during the time of the plasma CVD, optical interference is eventually induced when the incident ray transmits the DARC layer 32 and the reflection is lessened to the max. possible extent. In such a case, the inlet of the incident ray 40 eventually forms a reflected ray 43 and a reflected ray 44. Similarly, the DARC layer 32 gives rise to absorption and phase fluctuation in the reflected ray 44 and as a result thereof, the phase fluctuation does not eventually occur when the reflected ray 44 is coupled to the reflected ray 43.
摘要翻译：要解决的问题：通过使用引导材料抗反射涂层（DARC）层，通过有效地控制在光刻方法的执行过程中遇到的反射光线的强度来防止与不期望的反射相关的问题的发生。解决方案：DARC层32通过等离子体CVD形成，其中使用通过蒸发沉积的SiH 4和H 2作为反应物在底漆涂层31上形成。 DARC层32由SixOyNz材料组成。如果compsn。的DARC层32是通过改变amts实现的。的材料组成。（x，y，z）通过调节等离子体CVD期间的反应气体的流速和处理时间，当入射光线透射DARC层32并且反射减小到最大值时，最终引起光学干涉。可能的程度在这种情况下，入射光线40的入口最终形成反射光线43和反射光线44.类似地，DARC层32引起反射光线44中的吸收和相位波动，结果是相位当反射光线44耦合到反射光线43时，不会发生波动。

7. 发明专利

JP2020174167A ダイオード構造及びその製造方法审中-公开
公开(公告)号：JP2020174167A
公开(公告)日：2020-10-22
申请号：JP2019079911
申请日：2019-04-19
申请人：台湾茂▲し▼電子股▲ふん▼有限公司 , MOSEL VITELIC INC.
发明人：翁宏達 , 邱雲貴 , 朱建仲
IPC分类号： H01L29/861 , H01L29/868 , H01L21/329 , H01L29/41 , H01L29/47 , H01L29/872
摘要：【課題】マージ型PINショットキーダイオード構造を小型化し、リーク特性を向上し、高周波要件を満たす。【解決手段】ダイオード構造1は、第1金属層10、第1導電型半導体層11、第2導電型半導体層12、トレンチ部13及び第2金属層14を備える。第1導電型半導体層は、第1金属層上に形成される。第2導電型半導体層は第1導電型半導体層上に形成される。第1導電型半導体層と第2導電型半導体層とは逆の導電型を有し、それらの間にPN接合が形成される。トレンチ部は、第2導電型半導体層及び第1導電型半導体層の中に形成される。第1接触面は、トレンチ部と第1導電型半導体層との間に形成され、第2接触面は、トレンチ部と第2導電型半導体層との間に形成される。第2金属層は、第2導電型半導体層及びトレンチ部の上に形成される。【選択図】図1

8. 发明专利

JP2001308157A METHOD OF AUTOMATICALLY ASSORTING WAFER HAVING FAILURE MODE 失效
公开(公告)号：JP2001308157A
公开(公告)日：2001-11-02
申请号：JP2000110311
申请日：2000-04-12
申请人： PROMOS TECHNOLOGIES INC , MOSEL VITELIC INC , SIEMENS AG
发明人： TEI KOBEN
IPC分类号： H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide a method for automatically assorting wafers having a failure mode included therein and a failure mode which is easy to discover a part to be improved. SOLUTION: A wafer is provided and is divided into a plurality of segments circumscribing a center from the inside to the outside of the wafer, and the wafer is tested to obtain test data. Data in the segment are obtained by the test data, and the both are compared to then squeeze the segment having the same fail mode.

9. 发明专利

JP2001217309A SEMICONDUCTOR DEVICE WITH VIAHOLE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2001217309A
公开(公告)日：2001-08-10
申请号：JP2000015633
申请日：2000-01-25
申请人： PROMOS TECHNOLOGIES INC , MOSEL VITELIC INC , SIEMENS AG
发明人： WANG JIAN-JIUN , KYU SHUEKI , CHIN SOKI , JANG SHIAN-YUAN
IPC分类号： H01L23/522 , H01L21/28 , H01L21/768
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device equipped with a viahole which is filled up with a metal plug completely arranged within the border of a wiring and improved in reliability. SOLUTION: This manufacturing method comprises a first process in which a first interlayer insulating film 17 is formed on a first wiring layer 16 formed on a semiconductor substrate 1, a second process in which the first interlayer insulating film 17 is planarized so as to make its top surface flush with that of the first wiring layer 16, a third process in which an etching stop layer 18 is formed on the first interlayer insulating film 17 and the first wiring layer 16, a fourth process in which an oxide film 19 is formed on the etching stop layer 18, and a fifth layer in which the oxide film 19 and the etching stop layer 18 are etched by two steps, and a viahole 9 is formed. The first wiring layer 16 can be connected through the intermediary of the viahole 9.

10. 发明专利

JP2001144172A METHOD OF MANUFACTURING SHALLOW TRENCH ISOLATION STRUCTURE 失效
公开(公告)号：JP2001144172A
公开(公告)日：2001-05-25
申请号：JP32199699
申请日：1999-11-12
申请人： PROMOS TECHNOLOGIES INC , MOSEL VITELIC INC , SIEMENS AG
发明人： MO HONRYO
IPC分类号： H01L21/76 , H01L21/318
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a shallow trench isolation structure which solves the corner effect problem and the problems arising from the corner effect, thereby improving the throughput. SOLUTION: A substrate 100 is provided, a pad oxide film 102 and a hard mask film 104 are formed on the substrate, the pad oxide film 102, the hard mask film 104 and the substrate are partly removed to form trenches 106 into the substrate, the substrate with the trenches is left in an ozone atmosphere and irradiated with UV to form a liner oxide film 108 along the surface of each trench, and insulation plugs 110a are filled in the trenches.

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