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1. 发明授权

US08385863B2 DC offset calibration for complex filters 有权
标题翻译：复杂滤波器的直流偏移校准
公开(公告)号：US08385863B2
公开(公告)日：2013-02-26
申请号：US12539504
申请日：2009-08-11
申请人： Sudhakar Kalakota , Mingdeng Chen
发明人： Sudhakar Kalakota , Mingdeng Chen
IPC分类号： H01Q11/12 , H04B1/04
CPC分类号： H03H11/22 , H03H2011/0494
摘要： Exemplary techniques for DC offset calibration for complex filters are disclosed. A complex filter is provided having a first calibration path circuit and a second calibration path circuit, each including a first and a second set of switches, respectively. The first set of switches is enabled during calibration mode and the second set of switches is enabled during normal operation mode such that the network characteristics of each calibration path circuit are substantially the same during both modes of operation. In one embodiment, the complex filter is a low pass filter.
摘要翻译：公开了用于复杂滤波器的DC偏移校准的示例性技术。提供了具有第一校准路径电路和第二校准路径电路的复合滤波器，每个包括第一和第二组开关。第一组开关在校准模式期间使能，而第二组开关在正常操作模式期间使能，使得每个校准路径电路的网络特性在两种操作模式下基本相同。在一个实施例中，复合滤波器是低通滤波器。

2. 发明申请

US20090219057A1 Systems and methods for determining an out of band signal 失效
标题翻译：用于确定带外信号的系统和方法
公开(公告)号：US20090219057A1
公开(公告)日：2009-09-03
申请号：US12038972
申请日：2008-02-28
申请人： Mingdeng Chen , Ari Valero-Lopez , Weiwei Mao
发明人： Mingdeng Chen , Ari Valero-Lopez , Weiwei Mao
IPC分类号： G11C27/02
CPC分类号： H04L25/06 , G11C27/024 , H04L7/0087
摘要： Various embodiments of the present invention provide systems and circuits that provide for out of band detection. As one example, an out of band detection circuit is disclosed that includes an input signal, a clock generation circuit, and a sampling circuit. The clock generation circuit receives the input signal and derives therefrom a sampling clock, and the sampling circuit is operable to sample the input signal at a time indicated by the sampling clock.
摘要翻译：本发明的各种实施例提供了提供带外检测的系统和电路。作为一个例子，公开了一种包括输入信号，时钟产生电路和采样电路的带外检测电路。时钟生成电路接收输入信号并从其中导出采样时钟，并且采样电路可操作以在由采样时钟指示的时间采样输入信号。

3. 发明授权

US08829954B2 Frequency divider circuit 有权
标题翻译：分频器电路
公开(公告)号：US08829954B2
公开(公告)日：2014-09-09
申请号：US13070252
申请日：2011-03-23
申请人： Mazhareddin Taghivand , Jafar Savoj , Mingdeng Chen
发明人： Mazhareddin Taghivand , Jafar Savoj , Mingdeng Chen
IPC分类号： H03B19/06 , H03B19/14 , H03K23/42 , H03K3/356
CPC分类号： H03K3/356182 , H03B19/14 , H03K23/425
摘要： A frequency divider circuit is described. The frequency divider circuit includes a first cross-coupling. The first cross-coupling includes a first cross-coupled transistor with a first gate. The first gate is separately biased. The first cross-coupling also includes a second cross-coupled transistor with a second gate. The second gate is separately biased. The first gate is coupled to the second cross-coupled transistor and the second gate is coupled to the first cross-coupled transistor.
摘要翻译：描述了分频器电路。分频器电路包括第一交叉耦合。第一交叉耦合包括具有第一栅极的第一交叉耦合晶体管。第一个门是单独的偏见。第一交叉耦合还包括具有第二栅极的第二交叉耦合晶体管。第二个门是分开的偏见。第一栅极耦合到第二交叉耦合晶体管，第二栅极耦合到第一交叉耦合晶体管。

4. 发明授权

US07573417B2 Multi-bit per stage pipelined analog to digital converters 失效
标题翻译：多级每级流水线模数转换器
公开(公告)号：US07573417B2
公开(公告)日：2009-08-11
申请号：US12025914
申请日：2008-02-05
申请人： James A. Bailey , Mingdeng Chen
发明人： James A. Bailey , Mingdeng Chen
IPC分类号： H03M1/38
CPC分类号： H03M1/167
摘要： Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide pipelined analog to digital converters. Such converters include a sub-converter and a residue amplifier. The sub-converter receives an analog input, and provides a digital representation of the analog input including a number of bits. A gain of the residue amplifier is controlled by selectably setting a group of switches. Each of the number of bits output from the sub-converter electrically controls a respective one of the switches.
摘要翻译：本发明的各种实施例提供了提供将模拟信号转换成数字信号的系统和电路。例如，本发明的各种实施例提供流水线模数转换器。这种转换器包括子转换器和残留放大器。子转换器接收模拟输入，并且提供包括多个位的模拟输入的数字表示。通过可选择地设置一组开关来控制残余放大器的增益。从子转换器输出的每个位数电控制相应的一个开关。

5. 发明授权

US07358802B2 Multi-phase techniques for tuning and/or measuring operations of an amplifier 失效
标题翻译：用于调谐和/或测量放大器操作的多相技术
公开(公告)号：US07358802B2
公开(公告)日：2008-04-15
申请号：US11295877
申请日：2005-12-07
申请人： Mingdeng Chen
发明人： Mingdeng Chen
IPC分类号： H03F1/02
CPC分类号： H03F3/45475 , H03F3/211 , H03F3/45968 , H03F2200/78 , H03F2203/45138 , H03F2203/45212 , H03F2203/45616
摘要： Certain embodiments of the present invention relate to techniques for tuning or measuring operational features of amplifiers, such as the transconductance of operational transconductance amplifiers (OTAs) and the gain of variable gain amplifiers (VGAs). Each technique employs (at least) two phases that involve the application of different input voltages. The results of the multiple phases are then combined to generate a final result that negates or reduces the effects of real-world properties such as finite output impedances and offset voltages.
摘要翻译：本发明的某些实施例涉及用于调谐或测量放大器的操作特征的技术，例如工作跨导放大器（OTA）的跨导和可变增益放大器（VGA）的增益。每种技术都使用（至少）两个相位来应用不同的输入电压。然后组合多个相的结果以产生否定或减少真实世界特性如有限输出阻抗和偏移电压的影响的最终结果。

6. 发明申请

US20110037506A1 DC OFFSET CALIBRATION FOR COMPLEX FILTERS 有权
标题翻译：用于复杂过滤器的DC偏移校准
公开(公告)号：US20110037506A1
公开(公告)日：2011-02-17
申请号：US12539504
申请日：2009-08-11
申请人： Sudhakar Kalakota , Mingdeng Chen
发明人： Sudhakar Kalakota , Mingdeng Chen
IPC分类号： H03L5/00
CPC分类号： H03H11/22 , H03H2011/0494
摘要： Exemplary techniques for DC offset calibration for complex filters are disclosed. A complex filter is provided having a first calibration path circuit and a second calibration path circuit, each including a first and a second set of switches, respectively. The first set of switches is enabled during calibration mode and the second set of switches is enabled during normal operation mode such that the network characteristics of each calibration path circuit are substantially the same during both modes of operation. In one embodiment, the complex filter is a low pass filter.
摘要翻译：公开了用于复杂滤波器的DC偏移校准的示例性技术。提供了具有第一校准路径电路和第二校准路径电路的复合滤波器，每个包括第一和第二组开关。第一组开关在校准模式期间使能，而第二组开关在正常操作模式期间使能，使得每个校准路径电路的网络特性在两种操作模式下都基本相同。在一个实施例中，复合滤波器是低通滤波器。

7. 发明申请

US20070126499A1 Multi-phase techniques for tuning and/or measuring operations of an amplifier 失效
标题翻译：用于调谐和/或测量放大器操作的多相技术
公开(公告)号：US20070126499A1
公开(公告)日：2007-06-07
申请号：US11295877
申请日：2005-12-07
申请人： Mingdeng Chen
发明人： Mingdeng Chen
IPC分类号： H03F1/02
CPC分类号： H03F3/45475 , H03F3/211 , H03F3/45968 , H03F2200/78 , H03F2203/45138 , H03F2203/45212 , H03F2203/45616
摘要： Certain embodiments of the present invention relate to techniques for tuning or measuring operational features of amplifiers, such as the transconductance of operational transconductance amplifiers (OTAs) and the gain of variable gain amplifiers (VGAs). Each technique employs (at least) two phases that involve the application of different input voltages. The results of the multiple phases are then combined to generate a final result that negates or reduces the effects of real-world properties such as finite output impedances and offset voltages.
摘要翻译：本发明的某些实施例涉及用于调谐或测量放大器的操作特征的技术，例如工作跨导放大器（OTA）的跨导和可变增益放大器（VGA）的增益。每种技术都使用（至少）两个相位来应用不同的输入电压。然后组合多个相的结果以产生否定或减少真实世界特性（例如有限输出阻抗和偏移电压）的影响的最终结果。

8. 发明授权

US06927608B1 Low power low voltage differential signaling driver 有权
标题翻译：低功耗低压差分信号驱动器
公开(公告)号：US06927608B1
公开(公告)日：2005-08-09
申请号：US10655637
申请日：2003-09-05
申请人： Mingdeng Chen , Michael A. Nix
发明人： Mingdeng Chen , Michael A. Nix
IPC分类号： H03K17/687 , H03K3/00
CPC分类号： H03K17/6872
摘要： A low power LVDS driver includes a switchable current module, a source termination circuit, a transistor section, and a load current source. The switchable current module is operably coupled to produce a first current when a differential input signal is in a first state and to produce a second current when the differential input signal is in a second state. The source termination circuit is operably coupled in parallel with a load. The transistor section is operably coupled to receive the first and second currents from the switchable current module via at least one of the source termination circuit and the load, wherein the transistor section produces an LVDS output signal based on the first and second currents, the differential input signal, and the source termination circuit. The load current source is operably coupled to sink the first and second currents from the transistor section.
摘要翻译：低功率LVDS驱动器包括可切换电流模块，源极端接电路，晶体管部分和负载电流源。当差分输入信号处于第一状态时，可切换电流模块可操作地耦合以产生第一电流，并且当差分输入信号处于第二状态时产生第二电流。源端接电路与负载并联操作耦合。晶体管部分可操作地耦合以经由源极端接电路和负载中的至少一个从可切换电流模块接收第一和第二电流，其中晶体管部分基于第一和第二电流产生LVDS输出信号，差分输入信号和源终端电路。负载电流源可操作地耦合以吸收来自晶体管部分的第一和第二电流。

9. 发明申请

US20120242378A1 FREQUENCY DIVIDER CIRCUIT 有权
标题翻译：频率分路电路
公开(公告)号：US20120242378A1
公开(公告)日：2012-09-27
申请号：US13070252
申请日：2011-03-23
申请人： Mazhareddin Taghivand , Jafar Savoj , Mingdeng Chen
发明人： Mazhareddin Taghivand , Jafar Savoj , Mingdeng Chen
IPC分类号： H03B19/14 , H01L27/088
CPC分类号： H03K3/356182 , H03B19/14 , H03K23/425
摘要： A frequency divider circuit is described. The frequency divider circuit includes a first cross-coupling. The first cross-coupling includes a first cross-coupled transistor with a first gate. The first gate is separately biased. The first cross-coupling also includes a second cross-coupled transistor with a second gate. The second gate is separately biased. The first gate is coupled to the second cross-coupled transistor and the second gate is coupled to the first cross-coupled transistor.
摘要翻译：描述了分频器电路。分频器电路包括第一交叉耦合。第一交叉耦合包括具有第一栅极的第一交叉耦合晶体管。第一个门是单独的偏见。第一交叉耦合还包括具有第二栅极的第二交叉耦合晶体管。第二个门是分开的偏见。第一栅极耦合到第二交叉耦合晶体管，第二栅极耦合到第一交叉耦合晶体管。

10. 发明申请

US20090128389A1 Multi-bit Per Stage Pipelined Analog to Digital Converters 失效
标题翻译：多级位流水线模数转换器
公开(公告)号：US20090128389A1
公开(公告)日：2009-05-21
申请号：US12025914
申请日：2008-02-05
申请人： James A. Bailey , Mingdeng Chen
发明人： James A. Bailey , Mingdeng Chen
IPC分类号： H03M1/38 , H03M1/12
CPC分类号： H03M1/167
摘要： Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide pipelined analog to digital converters. Such converters include a sub-converter and a residue amplifier. The sub-converter receives an analog input, and provides a digital representation of the analog input including a number of bits. A gain of the residue amplifier is controlled by selectably setting a group of switches. Each of the number of bits output from the sub-converter electrically controls a respective one of the switches.
摘要翻译：本发明的各种实施例提供了提供将模拟信号转换成数字信号的系统和电路。例如，本发明的各种实施例提供流水线模数转换器。这种转换器包括子转换器和残留放大器。子转换器接收模拟输入，并且提供包括多个位的模拟输入的数字表示。通过可选择地设置一组开关来控制残余放大器的增益。从子转换器输出的每个位数电控制相应的一个开关。

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