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1. 发明授权

US09355951B2 Interconnect layouts for electronic assemblies 有权
标题翻译：电子组件的互连布局
公开(公告)号：US09355951B2
公开(公告)日：2016-05-31
申请号：US12855598
申请日：2010-08-12
申请人： Huahung Kao , Shiann-Ming Liou
发明人： Huahung Kao , Shiann-Ming Liou
IPC分类号： H01L23/498 , H01L23/00
CPC分类号： H01L23/49838 , H01L23/49816 , H01L23/49827 , H01L24/14 , H01L24/16 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01038 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00
摘要： Embodiments of the present disclosure provide an apparatus including an electronic device and a substrate to receive the electronic device, the electronic device being electrically coupled to the substrate using a plurality of interconnect structures, the interconnect structures being arranged on the electronic device based at least in part on a layout of the substrate. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供了一种包括电子设备和用于接收电子设备的基板的设备，电子设备使用多个互连结构电耦合到基板，所述互连结构至少基于部分是衬底的布局。可以描述和/或要求保护其他实施例。

2. 发明授权

US09257410B2 Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate 有权
标题翻译：包含半导体衬底的封装组件，其中半导体衬底的表面的第一部分相对于半导体衬底的表面的第二部分凹陷，以在半导体衬底中形成凹陷区域
公开(公告)号：US09257410B2
公开(公告)日：2016-02-09
申请号：US13012644
申请日：2011-01-24
申请人： Albert Wu , Roawen Chen , Chung Chyung Han , Shiann-Ming Liou , Chien-Chuan Wei , Runzi Chang , Scott Wu , Chuan-Cheng Cheng
发明人： Albert Wu , Roawen Chen , Chung Chyung Han , Shiann-Ming Liou , Chien-Chuan Wei , Runzi Chang , Scott Wu , Chuan-Cheng Cheng
IPC分类号： H01L25/04 , H01L21/48 , H01L23/13 , H01L23/14 , H01L23/498 , H01L25/065 , H01L25/10 , H01L25/00 , H01L23/367 , H01L23/00
CPC分类号： H01L25/04 , H01L21/486 , H01L21/565 , H01L21/76877 , H01L21/76898 , H01L23/13 , H01L23/147 , H01L23/3677 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/09 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/13024 , H01L2224/14181 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/81193 , H01L2224/83904 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1515 , H01L2924/15153 , H01L2924/15156 , H01L2924/15159 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供了一种装置，包括具有第一表面的半导体衬底，与第一表面相对设置的第二表面，其中第一表面的至少一部分被凹入以形成半导体衬底的凹陷区域，以及形成在半导体衬底的凹陷区域中以在半导体衬底的第一表面和第二表面之间提供电或热路径的一个或多个通孔，以及耦合到半导体衬底的管芯，该管芯电耦合到形成在半导体衬底的凹陷区域中的一个或多个通孔。可以描述和/或要求保护其他实施例。

3. 发明授权

US09209163B2 Package-on-package structures 有权
标题翻译：封装封装结构
公开(公告)号：US09209163B2
公开(公告)日：2015-12-08
申请号：US13584027
申请日：2012-08-13
申请人： Huahung Kao , Shiann-Ming Liou
发明人： Huahung Kao , Shiann-Ming Liou
IPC分类号： H01L25/10 , H01L25/16 , H01L23/31 , H01L23/00 , H01L25/065
CPC分类号： H01L25/50 , H01L21/56 , H01L21/76898 , H01L23/3128 , H01L24/04 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/92 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2224/0401 , H01L2224/04042 , H01L2224/0557 , H01L2224/05624 , H01L2224/05647 , H01L2224/06181 , H01L2224/11849 , H01L2224/13022 , H01L2224/13025 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2224/81191 , H01L2224/81801 , H01L2224/838 , H01L2224/92247 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2225/1052 , H01L2225/1058 , H01L2225/107 , H01L2225/1088 , H01L2225/1094 , H01L2924/00014 , H01L2924/01029 , H01L2924/10253 , H01L2924/1433 , H01L2924/1436 , H01L2924/1437 , H01L2924/1438 , H01L2924/15311 , H01L2924/15321 , H01L2924/181 , H01L2924/1815 , H01L2924/18161 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/05552 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls.
摘要翻译：本公开的实施例提供了一种包装装置，包括底部包装和第二包装。第一包装包括基底层，其包括（i）顶侧和（ii）与顶侧相对的底侧。此外，顶侧限定基本平坦的表面。第一封装还包括耦合到衬底层的底侧的管芯。第二封装包括多排焊球，并且第二封装通过多排焊球附接到基板层的基本上平坦的表面。

4. 发明授权

US09123699B1 Formation of package pins in semiconductor packaging 有权
标题翻译：在半导体封装中形成封装引脚
公开(公告)号：US09123699B1
公开(公告)日：2015-09-01
申请号：US13312065
申请日：2011-12-06
申请人： Chenglin Liu , Huahung Kao , Shiann-Ming Liou
发明人： Chenglin Liu , Huahung Kao , Shiann-Ming Liou
IPC分类号： H01L21/00 , H01L21/44 , H01L23/48 , H01L23/495 , H01L23/31
CPC分类号： H01L23/48 , H01L23/31 , H01L23/3121 , H01L23/3128 , H01L23/495 , H01L23/49541 , H01L23/49582 , H01L23/49586 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2224/2919 , H01L2224/29294 , H01L2224/29339 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments provide a method of fabricating a semiconductor package, the method comprising forming a leadframe, wherein the leadframe includes an inner lead, and wherein a bottom surface of the inner lead comprises a first section and a second section; depositing an oxidation resistant material on the first section of the bottom surface of the inner lead; and forming an oxidation layer on the second section of the bottom surface of the inner lead, wherein the oxidation resistant material deposited on the first section of the bottom surface of the inner lead prevents the oxidation layer from forming on the first section of the bottom surface of the inner lead.
摘要翻译：实施例提供了一种制造半导体封装的方法，所述方法包括形成引线框架，其中所述引线框架包括内引线，并且其中所述内引线的底表面包括第一部分和第二部分; 在所述内引线的底表面的第一部分上沉积抗氧化材料; 以及在所述内引线的底面的第二部分上形成氧化层，其中沉积在所述内引线的底表面的第一部分上的抗氧化材料防止在所述底表面的第一部分上形成所述氧化层的内线。

5. 发明授权

US09034730B2 Recessed semiconductor substrates and associated techniques 有权
标题翻译：嵌入式半导体衬底及相关技术
公开(公告)号：US09034730B2
公开(公告)日：2015-05-19
申请号：US13015988
申请日：2011-01-28
申请人： Albert Wu , Roawen Chen , Chung Chyung Han , Shiann-Ming Liou , Chien-Chuan Wei , Runzi Chang , Scott Wu , Chuan-Cheng Cheng
发明人： Albert Wu , Roawen Chen , Chung Chyung Han , Shiann-Ming Liou , Chien-Chuan Wei , Runzi Chang , Scott Wu , Chuan-Cheng Cheng
IPC分类号： H01L21/762 , H01L25/04 , H01L21/48 , H01L23/13 , H01L23/14 , H01L23/498 , H01L25/065 , H01L25/10 , H01L25/00 , H01L23/367 , H01L23/00
CPC分类号： H01L25/04 , H01L21/486 , H01L21/565 , H01L21/76877 , H01L21/76898 , H01L23/13 , H01L23/147 , H01L23/3677 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/09 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/13024 , H01L2224/14181 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/81193 , H01L2224/83904 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1515 , H01L2924/15153 , H01L2924/15156 , H01L2924/15159 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供一种方法，包括提供半导体衬底，其具有（i）第一表面和（ii）与第一表面相对设置的第二表面，在半导体衬底的第一表面中形成一个或多个通孔一个或多个通孔最初仅通过半导体衬底的一部分而不到达第二表面，在半导体衬底的第一表面上形成电介质膜，在电介质膜上形成再分布层，再分配层电耦合连接到所述一个或多个通孔，将一个或多个管芯耦合到所述再分布层，形成模制化合物以封装所述一个或多个管芯的至少一部分，以及使所述半导体衬底的所述第二表面凹陷以暴露所述一个或多个通孔。可以描述和/或要求保护其他实施例。

6. 发明授权

US08673687B1 Etched hybrid die package 失效
标题翻译：蚀刻混合模具包装
公开(公告)号：US08673687B1
公开(公告)日：2014-03-18
申请号：US12772304
申请日：2010-05-03
申请人： Chenglin Liu , Shiann-Ming Liou
发明人： Chenglin Liu , Shiann-Ming Liou
IPC分类号： H01L21/00
CPC分类号： H01L21/4828 , H01L21/4832 , H01L23/3121 , H01L23/49503 , H01L23/49541 , H01L2224/32245 , H01L2224/48091 , H01L2224/48257 , H01L2224/73265 , H01L2924/00014 , H01L2924/00
摘要： An embodiment includes a method that includes encapsulating a die and at least a portion of a lead-frame in a mold to form a package body. At least one primary lead attached to the lead-frame extends from the package body. The method includes etching a feature to within a threshold in an exposed die pad. The exposed die pad comprises a first surface that is prepared for etching and a second surface opposite to the first surface and attached to the die. The method includes positioning the die within a footprint of the exposed die pad, connecting the die to at least one primary lead, and connecting the feature to the die.
摘要翻译：一个实施例包括一种方法，其包括将模具和引线框架的至少一部分封装在模具中以形成封装体。连接到引线框架的至少一个主引线从封装主体延伸。该方法包括将特征蚀刻到暴露的裸片焊盘内的阈值内。暴露的管芯焊盘包括准备用于蚀刻的第一表面和与第一表面相对并附接到管芯的第二表面。该方法包括将裸片定位在暴露的裸片焊盘的覆盖区内，将裸片连接到至少一个主引线，并将该特征连接到管芯。

7. 发明授权

US08637975B1 Semiconductor device having lead wires connecting bonding pads formed on opposite sides of a core region forming a shield area 有权
标题翻译：半导体器件具有连接形成在形成屏蔽区域的芯区域的相对侧上的接合焊盘的引线
公开(公告)号：US08637975B1
公开(公告)日：2014-01-28
申请号：US13601442
申请日：2012-08-31
申请人： Shiann-Ming Liou
发明人： Shiann-Ming Liou
IPC分类号： H01L23/48
CPC分类号： H01L23/49816 , H01L23/5225 , H01L23/5286 , H01L23/60 , H01L23/645 , H01L24/05 , H01L24/06 , H01L24/09 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/0603 , H01L2224/06051 , H01L2224/0612 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/4813 , H01L2224/48247 , H01L2224/48465 , H01L2224/48471 , H01L2224/48479 , H01L2224/48599 , H01L2224/48699 , H01L2224/48799 , H01L2224/4911 , H01L2224/49112 , H01L2224/49175 , H01L2224/85051 , H01L2224/85201 , H01L2224/85205 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01077 , H01L2924/01079 , H01L2924/01082 , H01L2924/10161 , H01L2924/14 , H01L2924/3025 , H01L2224/48227 , H01L2924/00 , H01L2224/4554
摘要： A semiconductor device includes a semiconductor die. The semiconductor die includes a first bond pad having a plurality of connection points, the first bond pad arranged on a first portion of the semiconductor die, wherein the first portion corresponds to an outer periphery of the semiconductor die, and a second bond pad and a third bond pad arranged within a second portion of the semiconductor die, wherein the second portion is within the outer periphery of the semiconductor die. A lead external to the semiconductor die is configured to provide a voltage potential to the semiconductor die. A first lead wire is connected between the lead and a first connection point. A second lead wire is connected between the second bond pad and a second connection point. A third lead wire is connected between the third bond pad and a third connection point.
摘要翻译：半导体器件包括半导体管芯。半导体管芯包括具有多个连接点的第一接合焊盘，第一接合焊盘布置在半导体管芯的第一部分上，其中第一部分对应于半导体管芯的外周，第二接合焊盘和第三接合焊盘，其布置在所述半导体管芯的第二部分内，其中所述第二部分在所述半导体管芯的外周中。半导体管芯外部的引线被配置为向半导体管芯提供电压电位。第一引线连接在引线和第一连接点之间。第二引线连接在第二接合焊盘和第二连接点之间。第三引线连接在第三接合焊盘和第三连接点之间。

8. 发明申请

US20120196407A1 SINGLE LAYER BGA SUBSTRATE PROCESS 有权
标题翻译：单层BGA基板工艺
公开(公告)号：US20120196407A1
公开(公告)日：2012-08-02
申请号：US13358405
申请日：2012-01-25
申请人： Shiann-Ming Liou , Huahung Kao
发明人： Shiann-Ming Liou , Huahung Kao
IPC分类号： H01L21/50
CPC分类号： H01L21/50 , H01L21/4832 , H01L21/486 , H01L23/49816 , H01L23/49861 , H01L2224/48091 , H01L2924/09701 , H01L2924/15311 , H01L2924/00014
摘要： Embodiments of the present disclosure provide semiconductor packaging techniques that form a substrate using metal and insulating materials. The substrate includes a first surface that is bonded to a semiconductor device and a second surface that is bonded to a printed circuit board. The substrate is formed using several techniques that minimize the amount of mask levels used to form the substrate. For example, a metal substrate is patterned to form a three dimensional pattern on the surface. A dielectric material is deposited on the three dimensional pattern. Using several patterning and polishing embodiments described herein, the metal/dielectric substrate is patterned and polished to form a substantially flush surface that is bonded to the semiconductor device. In one embodiment, the top surface of the metal/dielectric substrate is patterned to expose the underlying metal substrate and the bottom surface of the metal substrate is polished to be substantially flush with the dielectric material.
摘要翻译：本公开的实施例提供了使用金属和绝缘材料形成衬底的半导体封装技术。基板包括接合到半导体器件的第一表面和结合到印刷电路板的第二表面。使用几种最小化用于形成衬底的掩模水平的量的技术来形成衬底。例如，将金属基板图案化以在表面上形成三维图案。介电材料沉积在三维图案上。使用本文所述的几种图案化和抛光实施例，金属/电介质基板被图案化和抛光以形成结合到半导体器件的基本上平齐的表面。在一个实施例中，金属/电介质基板的顶表面被图案化以暴露下面的金属基底，金属基底的底表面被抛光以与电介质材料基本齐平。

9. 再颁专利

USRE42853E1 Method and apparatus for coding an image object of arbitrary shape 有权
标题翻译：用于编码任意形状的图像对象的方法和装置
公开(公告)号：USRE42853E1
公开(公告)日：2011-10-18
申请号：US11561770
申请日：2006-11-20
申请人： Guobin Shen , Bing Zeng , Ming Liou
发明人： Guobin Shen , Bing Zeng , Ming Liou
IPC分类号： G06K9/36 , G06K9/46 , G06K9/34
CPC分类号： H04N19/649 , H04N19/20 , H04N19/61
摘要： It is known to represent a square block of an image which has a maximum horizontal or vertical extension N as N vectors each representing one column or row, and encode it using an N×N discrete cosine transform matrix. We introduce a technique which transforms an input vector, or array, representing a portion of an arbitrarily-shaped object block in which the maximum horizontal or vertical extension is at most N, by adding to it additional padding elements, to produce a vector or array which can be encoded using an N×N discrete cosine transform. The padding maximises the number of transformed elements which are zero. We propose encoding arbitrarily-shaped objects based on this padding technique.
摘要翻译：已知表示具有最大水平或垂直扩展N作为每个表示一列或多行的N个向量的图像的平方块，并且使用N×N个离散余弦变换矩阵进行编码。我们引入一种技术，其通过向其附加额外的填充元素来变换表示最大水平或垂直扩展最多为N的任意形状的对象块的一部分的输入向量或数组，以产生向量或数组其可以使用N×N离散余弦变换进行编码。填充最大化变换元素的数量为零。我们提出基于这种填充技术对任意形状的对象进行编码。

10. 发明申请

US20110186992A1 RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES 有权
标题翻译：残留的半导体衬底和相关技术
公开(公告)号：US20110186992A1
公开(公告)日：2011-08-04
申请号：US13015988
申请日：2011-01-28
申请人： Albert Wu , Roawen Chen , Chung Chyung Han , Shiann-Ming Liou , Chien-Chuan Wei , Runzi Chang , Scott Wu , Chuan-Cheng Cheng
发明人： Albert Wu , Roawen Chen , Chung Chyung Han , Shiann-Ming Liou , Chien-Chuan Wei , Runzi Chang , Scott Wu , Chuan-Cheng Cheng
IPC分类号： H01L23/48 , H01L21/56
CPC分类号： H01L25/04 , H01L21/486 , H01L21/565 , H01L21/76877 , H01L21/76898 , H01L23/13 , H01L23/147 , H01L23/3677 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/09 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/13024 , H01L2224/14181 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/81193 , H01L2224/83904 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1515 , H01L2924/15153 , H01L2924/15156 , H01L2924/15159 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供一种方法，包括提供半导体衬底，其具有（i）第一表面和（ii）与第一表面相对设置的第二表面，在半导体衬底的第一表面中形成一个或多个通孔一个或多个通孔最初仅通过半导体衬底的一部分而不到达第二表面，在半导体衬底的第一表面上形成电介质膜，在电介质膜上形成再分布层，再分配层电耦合连接到所述一个或多个通孔，将一个或多个管芯耦合到所述再分布层，形成模制化合物以封装所述一个或多个管芯的至少一部分，以及使所述半导体衬底的所述第二表面凹陷以暴露所述一个或多个通孔。可以描述和/或要求保护其他实施例。

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