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1. 发明授权

US5571731A Procedure for the manufacture of bipolar transistors without epitaxy and with fully implanted base and collector regions which are self-positioning relative to each other 失效
标题翻译：用于制造没有外延的双极晶体管和相对于彼此自定位的完全注入的基极和集电极区域的方法
公开(公告)号：US5571731A
公开(公告)日：1996-11-05
申请号：US215187
申请日：1994-03-21
申请人： Hartmut Gr utzediek , Joachim Scheerer , Wolfgang Winkler , Michel Pierschel , Karl-Ernst Ehwald
发明人： Hartmut Gr utzediek , Joachim Scheerer , Wolfgang Winkler , Michel Pierschel , Karl-Ernst Ehwald
IPC分类号： H01L21/331 , H01L29/732 , H01L21/265 , H01L21/00 , H01L21/30 , H01R21/22
CPC分类号： H01L29/66272 , H01L29/732
摘要： A method of fabricating a semiconductor device. A series of layers is deposited on a semiconductor substrate of a first conductivity type to form a shielding arrangement, including an upper part and a lower part, to provide a shield against accelerated ions. This is followed by forming openings in the shielding arrangement by microlithographic processes and anisotropic etching, and then implanting ions via the openings to form one of a base area and a base-connection area of the first conductivity type. Edges of the openings are displaced by isotropic etching of the lower part of the shielding arrangement. Ions are implanted which have been accelerated to energies sufficient to penetrate the one of the base area and base-connection area and a portion of the substrate underlying the one of the base area and base-connection area to form a sub-collector and a graded collector of a second conductivity type for completely encircling and separating a base from the substrate, wherein the sub-collector is more heavily doped than the collector. The base is formed by one of (i) implanting ions between the step of forming openings and the step of implanting ions accelerated, and (ii) implanting ions after the step of implanting ions accelerated. The method further includes forming an emitter, depositing an insulating layer, forming contacts to the base, the emitter and the collector, and forming a metalization arrangement.
摘要翻译：一种制造半导体器件的方法。一系列层沉积在第一导电类型的半导体衬底上，以形成包括上部和下部的屏蔽装置，以提供防止加速离子的屏蔽。然后通过微光刻和各向异性蚀刻在屏蔽装置中形成开口，然后通过开口注入离子以形成第一导电类型的基极区域和基极连接区域之一。通过对屏蔽装置的下部进行各向同性蚀刻来移动开口的边缘。被植入的离子被加速到足以穿透基底区域和基底连接区域中的一个的能量以及基底区域和基底连接区域之一的基底的一部分以形成子收集器和分级用于完全环绕和分离基底与基底的第二导电类型的集电极，其中子集电极比集电极更重掺杂。基底由（i）在形成开口的步骤和注入离子加速的步骤之间注入离子，和（ii）在植入离子加速的步骤之后注入离子之一形成。该方法还包括形成发射极，沉积绝缘层，与基底，发射极和集电极形成触点，并形成金属化装置。

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