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1. 发明授权

US5371894A Off-chip breakpoint system for a pipelined microprocessor 失效
标题翻译：流水线微处理器的片外断点系统
公开(公告)号：US5371894A
公开(公告)日：1994-12-06
申请号：US171985
申请日：1993-12-23
申请人： Michael T. DiBrino
发明人： Michael T. DiBrino
IPC分类号： G06F11/28 , G06F11/00 , G06F11/36
CPC分类号： G06F11/362
摘要： The invention is a system and method for providing a breakpoint exception at any predetermined instruction address in a processor system of the type including an integrated circuit microprocessor and an instruction cache and memory management unit (CMMU) where code addresses are sent to the instruction CMMU and the instruction CMMU returns with code instructions and returns with a FAULT code reply signal when there is no reply code, and wherein an exception is forced in the microprocessor in response to the FAULT code reply signal. The system comprises at least one breakpoint register for storing a predetermined breakpoint address, a means for comparing the code addresses which are sent to the CMMU with the predetermined breakpoint address in the breakpoint register and for generating a match signal when equivalent addresses are detected, and a means coupled to the CMMU and responsive to said match signal for causing said CMMU to issue a FAULT code reply signal, whereby an exception is forced in the microprocessor. The system is especially suitable for use with the Motorola MC88100 processor and MC88200 CMMU.
摘要翻译：本发明是一种用于在包括集成电路微处理器和指令高速缓存和存储器管理单元（CMMU）的类型的处理器系统中的任何预定指令地址处提供断点异常的系统和方法，其中代码地址被发送到指令CMMU，当没有应答码时，指令CMMU返回与代码指令并返回FAULT代码回复信号，并且其中响应于FAULT代码应答信号强制在微处理器中异常。该系统包括用于存储预定断点地址的至少一个断点寄存器，用于将发送到CMMU的代码地址与断点寄存器中的预定断点地址进行比较并在检测到等效地址时产生匹配信号的装置，以及耦合到CMMU并响应于所述匹配信号的装置，用于使所述CMMU发出FAULT代码应答信号，从而在微处理器中强制出现异常。该系统特别适用于摩托罗拉MC88100处理器和MC88200 CMMU。

2. 发明授权

US5581734A Multiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacity 失效
标题翻译：具有共享缓存和数据输入/输出电路的多处理器系统，用于传输数据量大于系统总线容量
公开(公告)号：US5581734A
公开(公告)日：1996-12-03
申请号：US101144
申请日：1993-08-02
申请人： Michael T. DiBrino , Dwain A. Hicks , George M. Lattimore , Kimming K. So , Hanaa Youssef
发明人： Michael T. DiBrino , Dwain A. Hicks , George M. Lattimore , Kimming K. So , Hanaa Youssef
IPC分类号： G06F12/08 , G06F15/167
CPC分类号： G06F12/0879 , G06F12/084 , G06F12/0855 , G06F12/0851
摘要： A high performance shared cache is provided to support multiprocessor systems and allow maximum parallelism in accessing the cache by the processors, servicing one processor request in each machine cycle, reducing system response time and increasing system throughput. The shared cache of the present invention uses the additional performance optimization techniques of pipelining cache operations (loads and stores) and burst-mode data accesses. By including built-in pipeline stages, the cache is enabled to service one request every machine cycle from any processing element. This contributes to reduction in the system response time as well as the throughput. With regard to the burst-mode data accesses, the widest possible data out of the cache can be stored to, and retrieved from, the cache by one cache access operation. One portion of the data is held in logic in the cache (on the chip), while another portion (corresponding to the system bus width) gets transferred to the requesting element (processor or memory) in one cycle. The held portion of the data can then be transferred in the following machine cycle.
摘要翻译：提供高性能共享缓存以支持多处理器系统，并允许处理器访问缓存的最大并行性，在每个机器周期中服务一个处理器请求，减少系统响应时间并提高系统吞吐量。本发明的共享缓存使用流水线高速缓存操作（加载和存储）和突发模式数据访问的附加性能优化技术。通过包括内置的流水线阶段，缓存可以从每个机器周期从任何处理元素服务一个请求。这有助于减少系统响应时间以及吞吐量。关于突发模式数据访问，可以通过一次高速缓存访问操作将高速缓存中的尽可能多的数据存储到高速缓冲存储器中并从高速缓存中检索出来。数据的一部分保存在高速缓存（芯片上）的逻辑中，而另一部分（对应于系统总线宽度）在一个周期内被传送到请求元件（处理器或存储器）。然后可以在以下机器周期中传送保存的数据部分。

3. 发明授权

US5379434A Apparatus and method for managing interrupts in a multiprocessor system 失效
标题翻译：用于管理多处理器系统中的中断的装置和方法
公开(公告)号：US5379434A
公开(公告)日：1995-01-03
申请号：US258127
申请日：1994-06-10
申请人： Michael T. DiBrino
发明人： Michael T. DiBrino
IPC分类号： G06F15/16 , G06F9/48 , G06F13/26 , G06F15/177
CPC分类号： G06F9/4812 , G06F13/26
摘要： A system and method for selecting a processor to service interrupts in a multiprocessor system with processor individualized interrupt priority states. The interrupt priority information associated with the various processors is bit serially compared to select one or more processors of lowest interrupt priority status, Processor individualized identification information is then compared to reconcile when multiple processors have an identical interrupt priority level, The outcome is stored and immediately available for managing interrupts generated by I/O devices, In a preferred arrangement, the interrupt priority status of the selected processor is confirmed immediately before processing the service requests to compensate for any changes occurring during the period of the bit serial comparison.
摘要翻译：一种用于选择处理器来为具有处理器个性化中断优先级状态的多处理器系统中的中断服务的系统和方法。与各种处理器相关联的中断优先级信息被比较串行比较以选择一个或多个最低中断优先级状态的处理器，然后当多个处理器具有相同的中断优先级时，将个体化标识信息进行比较以进行协调。结果存储并立即可用于管理I / O设备产生的中断。在优选的布置中，在处理服务请求之前立即确认所选处理器的中断优先级状态，以补偿在位串行比较期间发生的任何改变。

4. 发明授权

US07937574B2 Precise counter hardware for microcode loops 失效
标题翻译：微码循环的精确计数器硬件
公开(公告)号：US07937574B2
公开(公告)日：2011-05-03
申请号：US11778936
申请日：2007-07-17
申请人： Michael T. Clark , Jelena Ilic , Syed Faisal Ahmed , Michael T. DiBrino
发明人： Michael T. Clark , Jelena Ilic , Syed Faisal Ahmed , Michael T. DiBrino
IPC分类号： G06F9/26
CPC分类号： G06F9/325 , G06F9/264 , G06F9/3017 , G06F9/3802 , G06F9/382 , G06F9/3842 , G06F9/3867
摘要： In an embodiment, a microcode unit for a processor is contemplated. The microcode unit comprises a microcode memory storing a plurality of microcode routines executable by the processor, wherein each microcode routine comprises two or more microcode operations. Coupled to the microcode memory, the sequence control unit is configured to control reading microcode operations from the microcode memory to be issued for execution by the processor. The sequence control unit is configured to stall issuance of microcode operations forming a body of a loop in a first routine of the plurality of microcode routines until a loop counter value that indicates a number of iterations of the loop is received by the sequence control unit.
摘要翻译：在一个实施例中，预期用于处理器的微代码单元。微代码单元包括存储可由处理器执行的多个微代码例程的微代码存储器，其中每个微代码程序包括两个或多个微代码操作。耦合到微代码存储器，顺序控制单元被配置为控制从微代码存储器读取微代码操作以供处理器执行。顺序控制单元被配置为阻止在多个微代码例程的第一程序中形成循环体的微码操作的发布，直到由序列控制单元接收到指示循环的迭代次数的循环计数值。

5. 发明申请

US20090024842A1 Precise Counter Hardware for Microcode Loops 失效
标题翻译：微码循环的精确计数器硬件
公开(公告)号：US20090024842A1
公开(公告)日：2009-01-22
申请号：US11778936
申请日：2007-07-17
申请人： Michael T. Clark , Jelena Ilic , Syed Faisal Ahmed , Michael T. DiBrino
发明人： Michael T. Clark , Jelena Ilic , Syed Faisal Ahmed , Michael T. DiBrino
IPC分类号： G06F9/315
CPC分类号： G06F9/325 , G06F9/264 , G06F9/3017 , G06F9/3802 , G06F9/382 , G06F9/3842 , G06F9/3867
摘要： In an embodiment, a microcode unit for a processor is contemplated. The microcode unit comprises a microcode memory storing a plurality of microcode routines executable by the processor, wherein each microcode routine comprises two or more microcode operations. Coupled to the microcode memory, the sequence control unit is configured to control reading microcode operations from the microcode memory to be issued for execution by the processor. The sequence control unit is configured to stall issuance of microcode operations forming a body of a loop in a first routine of the plurality of microcode routines until a loop counter value that indicates a number of iterations of the loop is received by the sequence control unit.
摘要翻译：在一个实施例中，预期用于处理器的微代码单元。微代码单元包括存储可由处理器执行的多个微代码例程的微代码存储器，其中每个微代码程序包括两个或多个微代码操作。耦合到微代码存储器，顺序控制单元被配置为控制从微代码存储器读取微代码操作以供处理器执行。顺序控制单元被配置为阻止在多个微代码例程的第一程序中形成循环体的微码操作的发布，直到由序列控制单元接收到指示循环的迭代次数的循环计数值。

6. 发明授权

US5920489A Method and system for modeling the behavior of a circuit 失效
标题翻译：用于对电路行为进行建模的方法和系统
公开(公告)号：US5920489A
公开(公告)日：1999-07-06
申请号：US642292
申请日：1996-05-03
申请人： Michael T. Dibrino , David M. Wu
发明人： Michael T. Dibrino , David M. Wu
IPC分类号： G06F11/26 , G06F11/267 , G06F17/50 , G06F9/455
CPC分类号： G06F11/2215 , G06F17/5022 , G06F11/261
摘要： A method and system for modeling the behavior of a circuit are disclosed. A list specifying a plurality of transistors within the circuit and interconnections between the plurality of transistors is provided. Each fan node within the circuit is identified, where a fan node is defined as a point of interconnection between two or more of the plurality of transistors from which multiple nonredundant current paths to power, ground, or an input of the circuit exist. A fan node equation set is constructed that expresses a logical state of each fan node of the circuit in response to various transistor gate signal states. In addition, an output node equation is constructed that expresses a logical state of an output node of the circuit in terms of selected fan node logical states and specified transistor gate signal states. In response to receipt of a set of states of inputs to the circuit, a logical state of the output node is determined utilizing the fan node equation set and the output equation in order to model behavior of the circuit.
摘要翻译：公开了一种用于对电路行为进行建模的方法和系统。提供了指定电路内的多个晶体管和多个晶体管之间的互连的列表。识别电路内的每个风扇节点，其中风扇节点被定义为多个晶体管中的两个或更多个晶体管之间的互连点，从该多个晶体管的多个非冗余电流路径到达电源，地或电路的输入。构造了响应于各种晶体管栅极信号状态来表示电路的每个风扇节点的逻辑状态的风扇节点方程组。另外，根据所选择的风扇节点逻辑状态和指定的晶体管栅极信号状态，构造输出节点方程，其表示电路的输出节点的逻辑状态。响应于接收到电路的一组输入状态，使用风扇节点方程组和输出方程来确定输出节点的逻辑状态，以便模拟电路的行为。

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