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2. 发明授权

US5581734A Multiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacity 失效
标题翻译：具有共享缓存和数据输入/输出电路的多处理器系统，用于传输数据量大于系统总线容量
公开(公告)号：US5581734A
公开(公告)日：1996-12-03
申请号：US101144
申请日：1993-08-02
申请人： Michael T. DiBrino , Dwain A. Hicks , George M. Lattimore , Kimming K. So , Hanaa Youssef
发明人： Michael T. DiBrino , Dwain A. Hicks , George M. Lattimore , Kimming K. So , Hanaa Youssef
IPC分类号： G06F12/08 , G06F15/167
CPC分类号： G06F12/0879 , G06F12/084 , G06F12/0855 , G06F12/0851
摘要： A high performance shared cache is provided to support multiprocessor systems and allow maximum parallelism in accessing the cache by the processors, servicing one processor request in each machine cycle, reducing system response time and increasing system throughput. The shared cache of the present invention uses the additional performance optimization techniques of pipelining cache operations (loads and stores) and burst-mode data accesses. By including built-in pipeline stages, the cache is enabled to service one request every machine cycle from any processing element. This contributes to reduction in the system response time as well as the throughput. With regard to the burst-mode data accesses, the widest possible data out of the cache can be stored to, and retrieved from, the cache by one cache access operation. One portion of the data is held in logic in the cache (on the chip), while another portion (corresponding to the system bus width) gets transferred to the requesting element (processor or memory) in one cycle. The held portion of the data can then be transferred in the following machine cycle.
摘要翻译：提供高性能共享缓存以支持多处理器系统，并允许处理器访问缓存的最大并行性，在每个机器周期中服务一个处理器请求，减少系统响应时间并提高系统吞吐量。本发明的共享缓存使用流水线高速缓存操作（加载和存储）和突发模式数据访问的附加性能优化技术。通过包括内置的流水线阶段，缓存可以从每个机器周期从任何处理元素服务一个请求。这有助于减少系统响应时间以及吞吐量。关于突发模式数据访问，可以通过一次高速缓存访问操作将高速缓存中的尽可能多的数据存储到高速缓冲存储器中并从高速缓存中检索出来。数据的一部分保存在高速缓存（芯片上）的逻辑中，而另一部分（对应于系统总线宽度）在一个周期内被传送到请求元件（处理器或存储器）。然后可以在以下机器周期中传送保存的数据部分。

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