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1. 发明申请

US20060227811A1 TCP engine 有权
公开(公告)号：US20060227811A1
公开(公告)日：2006-10-12
申请号：US11218727
申请日：2005-09-02
申请人： Muhammad Hussain , Imran Badr , Faisal Masood , Philip Dickinson , Richard Kessler , Daniel Katz , Michael Bertone , Robert Sanzone , Thomas Hummel , Gregg Bouchard
发明人： Muhammad Hussain , Imran Badr , Faisal Masood , Philip Dickinson , Richard Kessler , Daniel Katz , Michael Bertone , Robert Sanzone , Thomas Hummel , Gregg Bouchard
IPC分类号： H04J3/06
CPC分类号： H04L69/16 , H04L49/90 , H04L49/9047 , H04L69/163
摘要： A network transport layer accelerator accelerates processing of packets so that packets can be forwarded at wire-speed. To accelerate processing of packets, the accelerator performs pre-processing on a network transport layer header encapsulated in a packet for a connection and performs in-line network transport layer checksum insertion prior to transmitting a packet. A timer unit in the accelerator schedules processing of the received packets. The accelerator also includes a free pool allocator which manages buffers for storing the received packets and a packet order unit which synchronizes processing of received packets for a same connection.

2. 发明申请

US20060059286A1 Multi-core debugger 审中-公开
标题翻译：多核调试器
公开(公告)号：US20060059286A1
公开(公告)日：2006-03-16
申请号：US11042476
申请日：2005-01-25
申请人： Michael Bertone , David Carlson , Richard Kessler , Philip Dickinson , Muhammad Hussain , Trent Parker
发明人： Michael Bertone , David Carlson , Richard Kessler , Philip Dickinson , Muhammad Hussain , Trent Parker
IPC分类号： G06F13/24
CPC分类号： G06F12/084 , G06F9/30014 , G06F9/30043 , G06F9/30138 , G06F9/3824 , G06F9/383 , G06F11/3632 , G06F12/0804 , G06F12/0813 , G06F12/0815 , G06F12/0835 , G06F12/0875 , G06F12/0891 , G06F13/24 , G06F2212/6012 , G06F2212/6022
摘要： In a multi-core processor, a high-speed interrupt-signal interconnect allows more than one of the processors to be interrupted at substantially the same time. For example, a global signal interconnect is coupled to each of the multiple processors, each processor being configured to selectively provide an interrupt signal, or pulse thereon. Preferably, each of the processor cores is capable of pulsing the global signal interconnect during every clock cycle to minimize delay between a triggering event and its respective interrupt signal. Each of the multiple processors also senses, or samples the global signal interconnect, preferably during the same cycle within which the pulse was provided, to determine the existence of an interrupt signal. Upon sensing an interrupt signal, each of the multiple processors responds to it substantially simultaneously. For example, an interrupt signal sampled by each of the multiple processors causes each processor to invoke a debug handler routine.
摘要翻译：在多核处理器中，高速中断信号互连允许多个处理器在同一时间被中断。例如，全局信号互连耦合到多个处理器中的每一个，每个处理器被配置为选择性地提供中断信号或其上的脉冲。优选地，每个处理器内核能够在每个时钟周期期间脉冲全局信号互连以最小化触发事件与其各自的中断信号之间的延迟。多个处理器中的每一个还优选地在提供脉冲的相同周期内感测或采样全局信号互连，以确定中断信号的存在。在感测到中断信号时，多个处理器中的每一个基本上同时响应。例如，由多个处理器中的每一个采样的中断信号使每个处理器调用调试处理程序。

3. 发明授权

US06654858B1 Method for reducing directory writes and latency in a high performance, directory-based, coherency protocol 失效
标题翻译：在高性能，基于目录的一致性协议中减少目录写入和延迟的方法
公开(公告)号：US06654858B1
公开(公告)日：2003-11-25
申请号：US09652324
申请日：2000-08-31
申请人： David H. Asher , Brian Lilly , Richard E. Kessler , Michael Bertone
发明人： David H. Asher , Brian Lilly , Richard E. Kessler , Michael Bertone
IPC分类号： G06F1200
CPC分类号： G06F12/0817 , G06F12/0824
摘要： A computer system has a plurality of processors wherein each processor preferably has its own cache memory. Each processor or group of processors may have a memory controller that interfaces to a main memory. Each main memory includes a “directory” that maintains the directory coherence state of each block of that memory. One or more of the processors are members of a “local” group of processors. Processors outside a local group are referred to as “remote” processors with respect to that local group. Whenever a remote processor performs a memory reference for a particular block of memory, the processor that maintains the directory for that block normally updates the directory to reflect that the remote processor now has exclusive ownership of the block. However, memory references between processors within a local group do not result in directory writes. Instead, the cache memory of the local processor that initiated the memory requests places or updates a copy of the requested data in its cache memory and also sets associated tag control bits to reflect the same or similar information as would have been written to the directory. If a subsequent request is received for that same block, the local processor that previously accessed the block examines its cache for the associated tag control bits. Using those bits, that processor will determine that it currently has the block exclusive and provides the requested data to the new processor that is requesting the data.
摘要翻译：计算机系统具有多个处理器，其中每个处理器优选地具有其自己的高速缓冲存储器。每个处理器或处理器组可以具有与主存储器接口的存储器控制器。每个主存储器包括维护该存储器的每个块的目录一致状态的“目录”。一个或多个处理器是“本地”处理器组的成员。本地组外的处理器称为“本地组”的“远程”处理器。每当远程处理器执行特定内存块的内存引用时，维护该块的目录的处理器通常会更新目录，以反映远程处理器现在拥有该块的独占所有权。但是，本地组内处理器之间的内存引用不会导致目录写入。相反，启动存储器请求的本地处理器的高速缓存存储器将所请求的数据的副本放置或更新在其高速缓冲存储器中，并且还设置相关联的标签控制位以反映与已经写入目录的相同或相似的信息。如果接收到该相同块的后续请求，则先前访问该块的本地处理器检查其相关标签控制位的高速缓存。使用这些位，该处理器将确定其当前具有块排他性，并且向请求数据的新处理器提供所请求的数据。

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