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1. 发明授权

US07439575B2 Protection against in-process charging in silicon-oxide-nitride-oxide-silicon (SONOS) memories 有权
标题翻译：防止在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器中的过程中充电
公开(公告)号：US07439575B2
公开(公告)日：2008-10-21
申请号：US11065312
申请日：2005-02-23
申请人： Yakov Roizin , Efraim Aloni , Micha Gutman , Menachem Vofsy , Avi Ben-Gigi
发明人： Yakov Roizin , Efraim Aloni , Micha Gutman , Menachem Vofsy , Avi Ben-Gigi
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L23/552 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A pre-metal dielectric structure of a SONOS memory structure includes a UV light-absorbing film, which prevents the ONO structure from being electronically charged in response to UV irradiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer located over the SONOS memory structure, a light-absorbing structure located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the light-absorbing structure. The light-absorbing structure can be a continuous polysilicon or amorphous silicon layer. Alternately, the light-absorbing structure can include one or more patterned polysilicon layers. In another embodiment, the SONOS transistors include UV light absorbing polysilicon spacers.
摘要翻译： SONOS存储器结构的金属前介电结构包括UV光吸收膜，其防止ONO结构响应于紫外线照射而被电荷充电。在一个实施例中，预金属电介质结构包括位于SONOS存储器结构之上的第一预金属电介质层，位于第一预金属介电层上方的光吸收结构和位于第一金属前介电层上的第二预金属介电层光吸收结构。光吸收结构可以是连续的多晶硅或非晶硅层。或者，光吸收结构可以包括一个或多个图案化的多晶硅层。在另一个实施例中，SONOS晶体管包括UV光吸收多晶硅间隔物。

2. 发明申请

US20110121379A1 Three-Terminal Single Poly NMOS Non-Volatile Memory Cell With Shorter Program/Erase Times 有权
标题翻译：具有较短程序/擦除次数的三端单单多极NMOS非易失性存储单元
公开(公告)号：US20110121379A1
公开(公告)日：2011-05-26
申请号：US13011774
申请日：2011-01-21
申请人： Evgeny Pikhay , Micha Gutman , Yakov Roizin
发明人： Evgeny Pikhay , Micha Gutman , Yakov Roizin
IPC分类号： H01L29/788
CPC分类号： G11C16/0441 , G11C16/10 , H01L27/0207 , H01L27/11519 , H01L27/11521 , H01L27/11546 , H01L27/11558 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： A three terminal non-volatile memory (NVM) cell for a CMOS IC is formed by either a standard CMOS process flow or a slightly modified CMOS process flow. The NVM cell includes read and injection transistors that share a common floating gate. The floating gate includes a portion disposed over the channel region of the read transistor, a portion disposed over the channel region of the injection transistor, and a portion extending into an enlarged drain diffusion area away from the channel regions, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitances. The source/drain of the injection transistor are formed using different LDD implants to achieve faster program/erase. Alternatively, an optional CHE enhancing implant is added to the source/drain of the injection transistor to enhance CHE programming. Both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension.
摘要翻译：用于CMOS IC的三端非易失性存储器（NVM）单元通过标准CMOS工艺流程或略微修改的CMOS工艺流程形成。 NVM单元包括共享公共浮动栅极的读取和注入晶体管。浮置栅极包括设置在读取晶体管的沟道区域上的部分，设置在注入晶体管的沟道区域上的部分和延伸到远离沟道区域的扩大的漏极扩散区域的部分，由此栅极 - 漏极电容高于栅极至源极电容。注入晶体管的源极/漏极使用不同的LDD种植体形成，以实现更快的编程/擦除。或者，可选的CHE增强注入被添加到注入晶体管的源极/漏极，以增强CHE编程。引入HV LDD和LV LDD两种植入物，使LDD植入物在浮栅延伸下合并。

3. 发明授权

US07060627B2 Method of decreasing charging effects in oxide-nitride-oxide (ONO) memory arrays 失效
标题翻译：降低氧化物 - 氧化物（ONO）存储器阵列中的充电效应的方法
公开(公告)号：US07060627B2
公开(公告)日：2006-06-13
申请号：US10659042
申请日：2003-09-09
申请人： Micha Gutman , Yakov Roizin , Menachem Vofsy , Efraim Aloni , Avi Ben-Gigi , Fumihiko Noro , Masatoshi Arai , Nobuyoshi Takahashi , Koji Yoshida
发明人： Micha Gutman , Yakov Roizin , Menachem Vofsy , Efraim Aloni , Avi Ben-Gigi , Fumihiko Noro , Masatoshi Arai , Nobuyoshi Takahashi , Koji Yoshida
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833
摘要： A fieldless array includes a semiconductor substrate, a plurality of oxide-nitride-oxide (ONO) structures formed over the upper surface of the semiconductor substrate, and a plurality of word lines formed over the ONO structures, wherein each of the ONO structures is substantially covered by one of the word lines. The word lines (typically polysilicon) block UV irradiation during subsequent processing steps, thereby substantially preventing electrons from being trapped in the silicon nitride layer of the ONO structure. As a result, the threshold voltages of the fieldless array transistors do not severely increase as the width of the fieldless array transistors decrease.
摘要翻译：无场阵列包括半导体衬底，形成在半导体衬底的上表面上的多个氧化物 - 氮化物氧化物（ONO）结构，以及形成在ONO结构上的多个字线，其中每个ONO结构基本上被一条字线覆盖。字线（通常为多晶硅）在随后的处理步骤期间阻挡UV照射，从而基本上防止电子被捕获在ONO结构的氮化硅层中。结果，无栅阵列晶体管的阈值电压随着无栅阵列晶体管的宽度减小而不会严重增加。

4. 发明授权

US07016225B2 Four-bit non-volatile memory transistor and array 失效
标题翻译：四位非易失性存储晶体管和阵列
公开(公告)号：US07016225B2
公开(公告)日：2006-03-21
申请号：US10305403
申请日：2002-11-26
申请人： Yakov Roizin , Micha Gutman , Shimon Greenberg , Alfred Yankelevich
发明人： Yakov Roizin , Micha Gutman , Shimon Greenberg , Alfred Yankelevich
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , H01L27/115 , H01L29/7923
摘要： A non-volatile memory cell capable of storing more than two bits of information. The NVM cell includes a semiconductor region having a first conductivity type, and a plurality of field isolation regions located in the semiconductor region. Four or more source/drain regions are located in the semiconductor region adjacent to the field isolation regions, the source/drain regions having a second conductivity type, opposite the first conductivity type. The field isolation regions and the source drain regions laterally surround a channel region in the semiconductor region. A gate structure, including a floating gate structure and a control gate structure, extends over the channel region, portions of the field isolation regions and portions of the source/drain regions. The floating gate structure includes a plurality of charge trapping regions, wherein each of the charge trapping regions is located adjacent to a corresponding one of the source/drain regions.
摘要翻译：能够存储多于两位信息的非易失性存储单元。 NVM单元包括具有第一导电类型的半导体区域和位于半导体区域中的多个场隔离区域。四个或更多个源极/漏极区域位于与场隔离区域相邻的半导体区域中，源极/漏极区域具有与第一导电类型相反的第二导电类型。场隔离区域和源漏区域横向地围绕半导体区域中的沟道区域。包括浮置栅极结构和控制栅极结构的栅极结构在沟道区域，场隔离区的部分和源极/漏极区的部分之间延伸。浮置栅极结构包括多个电荷俘获区域，其中每个电荷俘获区域位于与源极/漏极区域中相应的一个相邻的位置。

5. 发明申请

US20050139903A1 Protection againts in-process charging in silicon-oxide-nitride-oxide-silicon (SONOS) memories 有权
标题翻译：保护在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器中再次进行过程充电
公开(公告)号：US20050139903A1
公开(公告)日：2005-06-30
申请号：US11065312
申请日：2005-02-23
申请人： Yakov Roizin , Efraim Aloni , Micha Gutman , Menachem Vofsy , Avi Ben-Gigi
发明人： Yakov Roizin , Efraim Aloni , Micha Gutman , Menachem Vofsy , Avi Ben-Gigi
IPC分类号： H01L21/8246 , H01L23/552 , H01L27/115 , H01L21/4763
CPC分类号： H01L27/11568 , H01L23/552 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A pre-metal dielectric structure of a SONOS memory structure includes a UV light-absorbing film, which prevents the ONO structure from being electronically charged in response to UV irradiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer located over the SONOS memory structure, a light-absorbing structure located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the light-absorbing structure. The light-absorbing structure can be a continuous polysilicon or amorphous silicon layer. Alternately, the light-absorbing structure can include one or more patterned polysilicon layers. In another embodiment, the SONOS transistors include UV light absorbing polysilicon spacers.
摘要翻译： SONOS存储器结构的金属前介电结构包括UV光吸收膜，其防止ONO结构响应于紫外线照射而被电荷充电。在一个实施例中，预金属电介质结构包括位于SONOS存储器结构之上的第一预金属电介质层，位于第一预金属介电层上方的光吸收结构和位于第一金属前介电层上的第二预金属介电层光吸收结构。光吸收结构可以是连续的多晶硅或非晶硅层。或者，光吸收结构可以包括一个或多个图案化的多晶硅层。在另一个实施例中，SONOS晶体管包括UV光吸收多晶硅间隔物。

6. 发明申请

US20050054161A1 Method of decreasing charging effects in oxide-nitride-oxide (ONO) memory arrays 失效
标题翻译：降低氧化物 - 氧化物（ONO）存储器阵列中的充电效应的方法
公开(公告)号：US20050054161A1
公开(公告)日：2005-03-10
申请号：US10659042
申请日：2003-09-09
申请人： Micha Gutman , Yakov Roizin , Menachem Vofsy , Efraim Aloni , Avi Ben-Gigi , Fumihiko Noro , Masatoshi Arai , Nobuyoshi Takahashi , Koji Yoshida
发明人： Micha Gutman , Yakov Roizin , Menachem Vofsy , Efraim Aloni , Avi Ben-Gigi , Fumihiko Noro , Masatoshi Arai , Nobuyoshi Takahashi , Koji Yoshida
IPC分类号： H01L21/336 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833
摘要： A fieldless array includes a semiconductor substrate, a plurality of oxide-nitride-oxide (ONO) structures formed over the upper surface of the semiconductor substrate, and a plurality of word lines formed over the ONO structures, wherein each of the ONO structures is substantially covered by one of the word lines. The word lines (typically polysilicon) block UV irradiation during subsequent processing steps, thereby substantially preventing electrons from being trapped in the silicon nitride layer of the ONO structure. As a result, the threshold voltages of the fieldless array transistors do not severely increase as the width of the fieldless array transistors decrease.
摘要翻译：无场阵列包括半导体衬底，形成在半导体衬底的上表面上的多个氧化物 - 氮化物氧化物（ONO）结构，以及形成在ONO结构上的多个字线，其中每个ONO结构基本上被一条字线覆盖。字线（通常为多晶硅）在随后的处理步骤期间阻挡UV照射，从而基本上防止电子被捕获在ONO结构的氮化硅层中。结果，无栅阵列晶体管的阈值电压随着无栅阵列晶体管的宽度减小而不会严重增加。

7. 发明授权

US08344440B2 Three-terminal single poly NMOS non-volatile memory cell with shorter program/erase times 有权
标题翻译：具有较短编程/擦除次数的三端单单多晶硅非易失性存储单元
公开(公告)号：US08344440B2
公开(公告)日：2013-01-01
申请号：US13011774
申请日：2011-01-21
申请人： Evgeny Pikhay , Micha Gutman , Yakov Roizin
发明人： Evgeny Pikhay , Micha Gutman , Yakov Roizin
IPC分类号： H01L29/788
CPC分类号： G11C16/0441 , G11C16/10 , H01L27/0207 , H01L27/11519 , H01L27/11521 , H01L27/11546 , H01L27/11558 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： A three terminal non-volatile memory (NVM) cell for a CMOS IC is formed by either a standard CMOS process flow or a slightly modified CMOS process flow. The NVM cell includes read and injection transistors that share a common floating gate. The floating gate includes a portion disposed over the channel region of the read transistor, a portion disposed over the channel region of the injection transistor, and a portion extending into an enlarged drain diffusion area away from the channel regions, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitances. The source/drain of the injection transistor are formed using different LDD implants to achieve faster program/erase. Alternatively, an optional CHE enhancing implant is added to the source/drain of the injection transistor to enhance CHE programming. Both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension.
摘要翻译：用于CMOS IC的三端非易失性存储器（NVM）单元通过标准CMOS工艺流程或略微修改的CMOS工艺流程形成。 NVM单元包括共享公共浮动栅极的读取和注入晶体管。浮置栅极包括设置在读取晶体管的沟道区域上的部分，设置在注入晶体管的沟道区域上的部分和延伸到远离沟道区域的扩大的漏极扩散区域的部分，由此栅极 - 漏极电容高于栅极至源极电容。注入晶体管的源极/漏极使用不同的LDD种植体形成，以实现更快的编程/擦除。或者，可选的CHE增强注入被添加到注入晶体管的源极/漏极，以增强CHE编程。引入HV LDD和LV LDD两种植入物，使LDD植入物在浮栅延伸下合并。

8. 发明授权

US06959920B2 Protection against in-process charging in silicon-oxide-nitride-oxide-silicon (SONOS) memories 失效
标题翻译：防止在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器中的过程中充电
公开(公告)号：US06959920B2
公开(公告)日：2005-11-01
申请号：US10659031
申请日：2003-09-09
申请人： Yakov Roizin , Efraim Aloni , Micha Gutman , Menachem Vofsy , Avi Ben-Gigi
发明人： Yakov Roizin , Efraim Aloni , Micha Gutman , Menachem Vofsy , Avi Ben-Gigi
IPC分类号： H01L21/8246 , H01L23/552 , H01L27/115 , H01L29/792
CPC分类号： H01L27/11568 , H01L23/552 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A pre-metal dielectric structure of a SONOS memory structure includes a UV light-absorbing film, which prevents the ONO structure from being electronically charged in response to UV irradiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer located over the SONOS memory structure, a light-absorbing structure located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the light-absorbing structure. The light-absorbing structure can be a continuous polysilicon or amorphous silicon layer. Alternately, the light-absorbing structure can include one or more patterned polysilicon layers. In another embodiment, the SONOS transistors include UV light absorbing polysilicon spacers.
摘要翻译： SONOS存储器结构的金属前介电结构包括UV光吸收膜，其防止ONO结构响应于紫外线照射而被电荷充电。在一个实施例中，预金属电介质结构包括位于SONOS存储器结构之上的第一预金属电介质层，位于第一预金属介电层上方的光吸收结构和位于第一金属前介电层上的第二预金属介电层光吸收结构。光吸收结构可以是连续的多晶硅或非晶硅层。或者，光吸收结构可以包括一个或多个图案化的多晶硅层。在另一个实施例中，SONOS晶体管包括UV光吸收多晶硅间隔物。

9. 发明申请

US20050051838A1 Protection against in-process charging in silicon-oxide-nitride-oxide-silicon (SONOS) memories 失效
公开(公告)号：US20050051838A1
公开(公告)日：2005-03-10
申请号：US10659031
申请日：2003-09-09
申请人： Yakov Roizin , Efraim Aloni , Micha Gutman , Menachem Vofsy , Avi Ben-Gigi
发明人： Yakov Roizin , Efraim Aloni , Micha Gutman , Menachem Vofsy , Avi Ben-Gigi
IPC分类号： H01L21/8246 , H01L23/552 , H01L27/115 , H01L29/792
CPC分类号： H01L27/11568 , H01L23/552 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A pre-metal dielectric structure of a SONOS memory structure includes a UV light-absorbing film, which prevents the ONO structure from being electronically charged in response to UV irradiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer located over the SONOS memory structure, a light-absorbing structure located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the light-absorbing structure. The light-absorbing structure can be a continuous polysilicon or amorphous silicon layer. Alternately, the light-absorbing structure can include one or more patterned polysilicon layers. In another embodiment, the SONOS transistors include UV light absorbing polysilicon spacers.

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