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1. 发明申请

US20120060067A1 APPARATUS AND METHOD OF AUTHENTICATING JOINT TEST ACTION GROUP (JTAG) 审中-公开
标题翻译：联合测试行动小组（JTAG）的设备及方法
公开(公告)号：US20120060067A1
公开(公告)日：2012-03-08
申请号：US13291324
申请日：2011-11-08
申请人： Yun-ho Youm , Mi-jung Noh , Hong-mook Choi , Xingguang Feng
发明人： Yun-ho Youm , Mi-jung Noh , Hong-mook Choi , Xingguang Feng
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31705 , G01R31/31719 , G01R31/318566 , G01R31/318588
摘要： In an apparatus including a joint test action group (JTAG) authentication device, and a JTAG authentication method using the apparatus, the apparatus includes a joint test action group (JTAG) authentication device, the apparatus comprising a JTAG access circuit that determines whether to access a JTAG-compliant device according to a predetermined protocol that governs the JTAG-compliant device and the apparatus, wherein the JTAG access circuit at least one of inactivates at least one of inner bus lines and inner units and activates the at least one of the inner bus lines and the inner units according to whether the JTAG-compliant device is accessed.
摘要翻译：在包括联合测试动作组（JTAG）认证装置的装置和使用该装置的JTAG认证方法中，该装置包括联合测试动作组（JTAG）认证装置，该装置包括确定是否存取的JTAG接入电路根据预定协议的JTAG兼容设备，其管理所述JTAG兼容设备和所述设备，其中所述JTAG接入电路至少一个使内部总线和内部单元中的至少一个失效，并激活所述内部总线线路和内部单元，根据是否访问JTAG兼容设备。

2. 发明授权

US07965836B2 Data cipher processors 有权
标题翻译：数据加密处理器
公开(公告)号：US07965836B2
公开(公告)日：2011-06-21
申请号：US11063912
申请日：2005-02-23
申请人： Kyoung-moon Ahn , Mi-jung Noh
发明人： Kyoung-moon Ahn , Mi-jung Noh
IPC分类号： H04L9/00
CPC分类号： H04L9/0631 , H04L9/003 , H04L2209/046 , H04L2209/24
摘要： Data cipher processors, advanced encryption standard (AES) cipher system, and AES cipher methods using a masking method perform round operations using a round key, a plain text, a cipher text, and masking data. Some of the round operations are implemented over a composite Galois Field GF(•). Original data and predetermined masking data are processed according to a predetermined rule. Sub-byte transformation operations used in the cipher method and system may include an affine transformation, an inverse affine transformation, an isomorphic transformation, and an inverse isomorphic transformation which are linear transformations, and an inverse transformation that is a non-linear transformation.
摘要翻译：数据加密处理器，高级加密标准（AES）密码系统和使用掩蔽方法的AES加密方法使用循环密钥，纯文本，密文和掩蔽数据执行轮回操作。一些循环操作通过组合Galois Field GF（•）实现。根据预定规则处理原始数据和预定掩蔽数据。在密码方法和系统中使用的子字节变换操作可以包括作为线性变换的仿射变换，逆仿射变换，同构变换和逆同构变换，以及作为非线性变换的逆变换。

3. 发明申请

US20100138467A1 METHODS OF CALCULATING NEGATIVE INVERSE OF MODULUS 有权
标题翻译：计算模态反演的方法
公开(公告)号：US20100138467A1
公开(公告)日：2010-06-03
申请号：US12618283
申请日：2009-11-13
申请人： Young-sik Kim , Mi-jung Noh , Kyoung-moon Ahn , Sun-soo Shin
发明人： Young-sik Kim , Mi-jung Noh , Kyoung-moon Ahn , Sun-soo Shin
IPC分类号： G06F7/72
CPC分类号： G06F7/72 , G06F7/721 , G06F7/728
摘要： Provided is a method of calculating a negative inverse of a modulus, wherein the negative inverse, which is an essential element in Montgomery multiplication, is quickly obtained. The method includes setting a modulus, defining P obtained by converting the modulus to a negative number, and defining S obtained by subtracting 1 from P, and calculating a negative inverse of the modulus by using P and S.
摘要翻译：提供了一种计算模数的负逆的方法，其中快速获得作为蒙哥马利乘法中的基本要素的负逆。该方法包括设定模量，通过将模数转换为负数来定义P，并定义通过从P中减去1获得的S，并且通过使用P和S计算模量的负逆。

4. 发明申请

US20090228977A1 PASSWORD SYSTEM, METHOD OF GENERATING A PASSWORD, AND METHOD OF CHECKING A PASSWORD 有权
标题翻译：密码系统，生成密码的方法和检查密码的方法
公开(公告)号：US20090228977A1
公开(公告)日：2009-09-10
申请号：US12398359
申请日：2009-03-05
申请人： Hyun-woong LEE , Mi-jung NOH , Hong-mook CHOI , Xingguang FENG
发明人： Hyun-woong LEE , Mi-jung NOH , Hong-mook CHOI , Xingguang FENG
IPC分类号： H04L9/32 , G06F21/00
CPC分类号： G06F21/46 , H04L9/3226
摘要： A password system includes a user interface, a password generating unit, and a password checking unit. The password generating unit generates a password including multiple frames, generates an integrity check code associated with the generated password, and scrambles the generated password and provides the scrambled password to the user interface. The password checking unit stores the integrity check code, frame number information and scramble information which are provided from the password generating unit, descrambles a scrambled password that is input from the user interface based on the stored scramble information, and authenticates the user interface by comparing an integrity check code generated from the descrambled password and the stored integrity check code.
摘要翻译：密码系统包括用户界面，密码生成单元和密码检查单元。密码生成单元生成包含多个帧的密码，生成与生成的密码相关联的完整性检查码，并且对生成的密码进行加扰，并将加扰的密码提供给用户界面。密码检查单元存储从密码生成单元提供的完整性校验码，帧号信息和加扰信息，根据存储的加扰信息解密从用户界面输入的扰码密码，并通过比较来认证用户界面从解扰密码和存储的完整性校验码产生的完整性校验码。

5. 发明申请

US20050207571A1 Data cipher processors, AES cipher systems, and AES cipher methods using a masking method 有权
标题翻译：数据加密处理器，AES密码系统和使用掩码法的AES密码方法
公开(公告)号：US20050207571A1
公开(公告)日：2005-09-22
申请号：US11063912
申请日：2005-02-23
申请人： Kyoung-moon Ahn , Mi-jung Noh
发明人： Kyoung-moon Ahn , Mi-jung Noh
IPC分类号： G09C1/00 , H04K1/00 , H04L9/06 , H04L9/08 , H04L9/10
CPC分类号： H04L9/0631 , H04L9/003 , H04L2209/046 , H04L2209/24
摘要： Data cipher processors, advanced encryption standard (AES) cipher system, and AES cipher methods using a masking method perform round operations using a round key, a plain text, a cipher text, and masking data. Some of the round operations are implemented over a composite Galois Field GF(•). Original data and predetermined masking data are processed according to a predetermined rule. Sub-byte transformation operations used in the cipher method and system may include an affine transformation, an inverse affine transformation, an isomorphic transformation, and an inverse isomorphic transformation which are linear transformations, and an inverse transformation that is a non-linear transformation.
摘要翻译：数据加密处理器，高级加密标准（AES）密码系统和使用掩蔽方法的AES加密方法使用循环密钥，纯文本，密文和掩蔽数据执行轮回操作。一些圆形操作通过复合Galois Field GF（。）实现。根据预定规则处理原始数据和预定掩蔽数据。在密码方法和系统中使用的子字节变换操作可以包括作为线性变换的仿射变换，逆仿射变换，同构变换和逆同构变换，以及作为非线性变换的逆变换。

6. 发明授权

US06324116B1 Merged semiconductor device having DRAM and SRAM and data transferring method using the semiconductor device 有权
标题翻译：具有DRAM和SRAM的合并半导体器件和使用该半导体器件的数据传输方法
公开(公告)号：US06324116B1
公开(公告)日：2001-11-27
申请号：US09595747
申请日：2000-06-16
申请人： Mi-jung Noh , Jeong-seok Lee
发明人： Mi-jung Noh , Jeong-seok Lee
IPC分类号： G11C800
CPC分类号： G06F12/0893 , G06F2212/3042
摘要： A merged semiconductor device having a DRAM and an SRAM, and a data transmitting method using the same are provided. In this device, the DRAM acts as a main memory, and the SRAM acts as a cache memory. The reading operation of the DRAM, and the writing operation of the SRAM are simultaneously controlled by a DRAM read control signal. Also, the writing operation of the DRAM, and the reading operation of the SRAM are simultaneously controlled by a DRAM write control signal. In this device, DRAM write commands and DRAM read commands can be continuously given. Writing of the SRAM starts after reading of the DRAM is completed, and writing of the DRAM starts after reading of the SRAM is completed.
摘要翻译：提供具有DRAM和SRAM的合并半导体器件以及使用其的数据发送方法。在该装置中，DRAM用作主存储器，并且SRAM充当高速缓冲存储器。 DRAM的读取操作和SRAM的写入操作由DRAM读取控制信号同时控制。此外，DRAM的写入操作和SRAM的读取操作由DRAM写入控制信号同时控制。在该装置中，可以连续地给出DRAM写入命令和DRAM读取命令。在完成DRAM的读取之后，SRAM的写入完成，并且在读取SRAM之后开始DRAM的写入。

7. 发明授权

US08291491B2 Password system, method of generating a password, and method of checking a password 有权
标题翻译：密码系统，生成密码的方法和密码检查方法
公开(公告)号：US08291491B2
公开(公告)日：2012-10-16
申请号：US12398359
申请日：2009-03-05
申请人： Hyun-woong Lee , Mi-jung Noh , Hong-mook Choi , Xingguang Feng
发明人： Hyun-woong Lee , Mi-jung Noh , Hong-mook Choi , Xingguang Feng
IPC分类号： G06F7/04
CPC分类号： G06F21/46 , H04L9/3226
摘要： A password system includes a user interface, a password generating unit, and a password checking unit. The password generating unit generates a password including multiple frames, generates an integrity check code associated with the generated password, and scrambles the generated password and provides the scrambled password to the user interface. The password checking unit stores the integrity check code, frame number information and scramble information which are provided from the password generating unit, descrambles a scrambled password that is input from the user interface based on the stored scramble information, and authenticates the user interface by comparing an integrity check code generated from the descrambled password and the stored integrity check code.
摘要翻译：密码系统包括用户界面，密码生成单元和密码检查单元。密码生成单元生成包含多个帧的密码，生成与生成的密码相关联的完整性检查码，并且对生成的密码进行加扰，并将加扰的密码提供给用户界面。密码检查单元存储从密码生成单元提供的完整性校验码，帧号信息和加扰信息，根据存储的加扰信息解密从用户界面输入的扰码密码，并通过比较来认证用户界面从解扰密码和存储的完整性校验码产生的完整性校验码。

8. 发明申请

US20050169463A1 Hardware cryptographic engine and hardware cryptographic method using an efficient S-BOX implementation 审中-公开
标题翻译：硬件加密引擎和硬件加密方法使用高效的S-BOX实现
公开(公告)号：US20050169463A1
公开(公告)日：2005-08-04
申请号：US11024855
申请日：2004-12-30
申请人： Kyoung-moon Ahn , Mi-jung Noh
发明人： Kyoung-moon Ahn , Mi-jung Noh
IPC分类号： G09C1/00 , H04K1/00 , H04L9/06 , H04L9/14
CPC分类号： H04L9/0631 , H04L2209/12 , H04L2209/24
摘要： A hardware cryptographic engine implementing an Advanced Encryption Standard (AES) algorithm is disclosed. The hardware cryptographic engine comprises a plurality of modules corresponding to rounds of AES. Each of the plurality of modules comprises an S-BOX computing a multiplicative inverse of each element in an input vector over GF(28) using an operation over GF(((22)2)2), and replacing each element of the input vector with a substitute element obtained using a result of the operation.
摘要翻译：公开了实现高级加密标准（AES）算法的硬件加密引擎。硬件加密引擎包括对应于AES循环的多个模块。多个模块中的每一个包括使用GF上的操作（（（2＆lt; 2＆gt; 2））来计算GF（2＆lt; 8＆gt; 8）上的输入向量中的每个元素的乘法逆的S-BOX， SUP>）^{2 ）^{2），并且用使用该操作结果获得的替代元素替换输入向量的每个元素。}}

9. 发明授权

US06538941B2 Semiconductor memory device and method of pre-charging I/O lines 有权
公开(公告)号：US06538941B2
公开(公告)日：2003-03-25
申请号：US09812072
申请日：2001-03-19
申请人： Mi-Jung Noh
发明人： Mi-Jung Noh
IPC分类号： G11C700
CPC分类号： G11C11/4097 , G11C7/1048 , G11C2207/002
摘要： There is provided a semiconductor memory device and a method of pre-charging I/O lines therein. Multiplexers are controlled in such a way as to disconnect their normally connected switches only when desired, thereby reducing the number of pre-charging means employed as compared to prior art devices and methods.

10. 发明授权

US08458242B2 Modular multiplier apparatus with reduced critical path of arithmetic operation and method of reducing the critical path of arithmetic operation in arithmetic operation apparatus 有权
标题翻译：具有降低运算运算关键路径的模块化乘法器和降低算术运算装置运算运算关键路径的方法
公开(公告)号：US08458242B2
公开(公告)日：2013-06-04
申请号：US12660382
申请日：2010-02-25
申请人： Young-sik Kim , Mi-jung Noh , Kyoung-moon Ahn , Sun-soo Shin
发明人： Young-sik Kim , Mi-jung Noh , Kyoung-moon Ahn , Sun-soo Shin
IPC分类号： G06F7/72
CPC分类号： G06F7/728
摘要： Provided are a modular multiplier apparatus in which a value of a long path carry (LPC) is predicted to reduce a critical path of an arithmetic operation of Montgomery modular multiplication, and a method of reducing the critical path of the arithmetic operation. The modular multiplier apparatus for obtaining a quotient and a result of an arithmetic operation of modular multiplication by using a modulus and two arbitrary constants includes: a reduction unit for obtaining a short path carry (SPC) included when a result of a modular arithmetic operation is obtained at a current stage, by using a medium calculation result; a carry predictor for predicting a long path carry (LPC) included when the result of the modular arithmetic operation is obtained at the current stage, by using the medium calculation result; and an accumulator for accumulating the result of the modular arithmetic operation by using the SPC and the LPC, wherein the medium calculation result is obtained by adding a result of a modular arithmetic operation obtained at a previous stage and a partial product of the two constants obtained at the current stage.
摘要翻译：提供了一种模数乘法器装置，其中预测长路径进位（LPC）的值以减少蒙哥马利乘法运算的关键路径，以及减少算术运算的关键路径的方法。用于通过使用模数和两个任意常数来获得商和乘法运算的结果的模乘法器包括：用于获得当模运算的结果为包括的短路径进位（SPC）的缩小单元是通过使用中等计算结果在当前阶段获得; 通过使用介质计算结果，当在当前阶段获得模数运算的结果时，预测包含的长路径进位（LPC）的进位预测器; 以及用于通过使用SPC和LPC累积模数运算结果的累加器，其中，通过将前一阶段获得的模运算结果和获得的两个常数的部分乘积相加得到介质计算结果在目前阶段。

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