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1. 发明授权

US08291491B2 Password system, method of generating a password, and method of checking a password 有权
标题翻译：密码系统，生成密码的方法和密码检查方法
公开(公告)号：US08291491B2
公开(公告)日：2012-10-16
申请号：US12398359
申请日：2009-03-05
申请人： Hyun-woong Lee , Mi-jung Noh , Hong-mook Choi , Xingguang Feng
发明人： Hyun-woong Lee , Mi-jung Noh , Hong-mook Choi , Xingguang Feng
IPC分类号： G06F7/04
CPC分类号： G06F21/46 , H04L9/3226
摘要： A password system includes a user interface, a password generating unit, and a password checking unit. The password generating unit generates a password including multiple frames, generates an integrity check code associated with the generated password, and scrambles the generated password and provides the scrambled password to the user interface. The password checking unit stores the integrity check code, frame number information and scramble information which are provided from the password generating unit, descrambles a scrambled password that is input from the user interface based on the stored scramble information, and authenticates the user interface by comparing an integrity check code generated from the descrambled password and the stored integrity check code.
摘要翻译：密码系统包括用户界面，密码生成单元和密码检查单元。密码生成单元生成包含多个帧的密码，生成与生成的密码相关联的完整性检查码，并且对生成的密码进行加扰，并将加扰的密码提供给用户界面。密码检查单元存储从密码生成单元提供的完整性校验码，帧号信息和加扰信息，根据存储的加扰信息解密从用户界面输入的扰码密码，并通过比较来认证用户界面从解扰密码和存储的完整性校验码产生的完整性校验码。

2. 发明申请

US20100153797A1 Apparatus and method of authenticating Joint Test Action Group (JTAG) 有权
标题翻译：联合测试行动小组（JTAG）认证的设备和方法
公开(公告)号：US20100153797A1
公开(公告)日：2010-06-17
申请号：US12653082
申请日：2009-12-08
申请人： Yun-ho Youm , Mi-jung Noh , Hong-mook Choi , Xingguang Feng
发明人： Yun-ho Youm , Mi-jung Noh , Hong-mook Choi , Xingguang Feng
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31705 , G01R31/31719 , G01R31/318566 , G01R31/318588
摘要： In an apparatus including a joint test action group (JTAG) authentication device, and a JTAG authentication method using the apparatus, the apparatus includes a joint test action group (JTAG) authentication device, the apparatus comprising a JTAG access circuit that determines whether to access a JTAG-compliant device according to a predetermined protocol that governs the JTAG-compliant device and the apparatus, wherein the JTAG access circuit at least one of inactivates at least one of inner bus lines and inner units and activates the at least one of the inner bus lines and the inner units according to whether the JTAG-compliant device is accessed.
摘要翻译：在包括联合测试动作组（JTAG）认证装置的装置和使用该装置的JTAG认证方法中，该装置包括联合测试动作组（JTAG）认证装置，该装置包括确定是否存取的JTAG接入电路根据预定协议的JTAG兼容设备，其管理所述JTAG兼容设备和所述设备，其中所述JTAG接入电路至少一个使内部总线和内部单元中的至少一个失效，并激活所述内部总线线路和内部单元，根据是否访问JTAG兼容设备。

3. 发明授权

US08056142B2 Apparatus and method of authenticating joint test action group (JTAG) 有权
标题翻译：认证联合测试动作组（JTAG）的设备和方法
公开(公告)号：US08056142B2
公开(公告)日：2011-11-08
申请号：US12653082
申请日：2009-12-08
申请人： Yun-ho Youm , Mi-jung Noh , Hong-mook Choi , Xingguang Feng
发明人： Yun-ho Youm , Mi-jung Noh , Hong-mook Choi , Xingguang Feng
IPC分类号： G06F7/04 , G06F17/30 , H04N7/16
CPC分类号： G01R31/31705 , G01R31/31719 , G01R31/318566 , G01R31/318588
摘要： In an apparatus including a joint test action group (JTAG) authentication device, and a JTAG authentication method using the apparatus, the apparatus includes a joint test action group (JTAG) authentication device, the apparatus comprising a JTAG access circuit that determines whether to access a JTAG-compliant device according to a predetermined protocol that governs the JTAG-compliant device and the apparatus, wherein the JTAG access circuit at least one of inactivates at least one of inner bus lines and inner units and activates the at least one of the inner bus lines and the inner units according to whether the JTAG-compliant device is accessed.
摘要翻译：在包括联合测试动作组（JTAG）认证装置的装置和使用该装置的JTAG认证方法中，该装置包括联合测试动作组（JTAG）认证装置，该装置包括确定是否存取的JTAG接入电路根据预定协议的JTAG兼容设备，其管理所述JTAG兼容设备和所述设备，其中所述JTAG接入电路至少一个使内部总线和内部单元中的至少一个失效，并激活所述内部总线线路和内部单元，根据是否访问JTAG兼容设备。

4. 发明申请

US20120060067A1 APPARATUS AND METHOD OF AUTHENTICATING JOINT TEST ACTION GROUP (JTAG) 审中-公开
标题翻译：联合测试行动小组（JTAG）的设备及方法
公开(公告)号：US20120060067A1
公开(公告)日：2012-03-08
申请号：US13291324
申请日：2011-11-08
申请人： Yun-ho Youm , Mi-jung Noh , Hong-mook Choi , Xingguang Feng
发明人： Yun-ho Youm , Mi-jung Noh , Hong-mook Choi , Xingguang Feng
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31705 , G01R31/31719 , G01R31/318566 , G01R31/318588
摘要： In an apparatus including a joint test action group (JTAG) authentication device, and a JTAG authentication method using the apparatus, the apparatus includes a joint test action group (JTAG) authentication device, the apparatus comprising a JTAG access circuit that determines whether to access a JTAG-compliant device according to a predetermined protocol that governs the JTAG-compliant device and the apparatus, wherein the JTAG access circuit at least one of inactivates at least one of inner bus lines and inner units and activates the at least one of the inner bus lines and the inner units according to whether the JTAG-compliant device is accessed.
摘要翻译：在包括联合测试动作组（JTAG）认证装置的装置和使用该装置的JTAG认证方法中，该装置包括联合测试动作组（JTAG）认证装置，该装置包括确定是否存取的JTAG接入电路根据预定协议的JTAG兼容设备，其管理所述JTAG兼容设备和所述设备，其中所述JTAG接入电路至少一个使内部总线和内部单元中的至少一个失效，并激活所述内部总线线路和内部单元，根据是否访问JTAG兼容设备。

5. 发明申请

US20110123020A1 ENDECRYPTOR CAPABLE OF PERFORMING PARALLEL PROCESSING AND ENCRYPTION/DECRYPTION METHOD THEREOF 有权
标题翻译：执行并行处理和加密/分解方法的后处理器
公开(公告)号：US20110123020A1
公开(公告)日：2011-05-26
申请号：US12874799
申请日：2010-09-02
申请人： Hong-Mook Choi , Jisoo Kim , Xingguang Feng , Woo-Hyun Lee
发明人： Hong-Mook Choi , Jisoo Kim , Xingguang Feng , Woo-Hyun Lee
IPC分类号： H04L9/28
CPC分类号： H04L9/0637 , H04L2209/125 , H04L2209/20
摘要： An encryption/decryption method of an endecryptor including a plurality of endecryption units supporting an XES mode with tweak and ciphertext streaming (XTS) includes dividing an input data stream into consecutive data units; inputting the divided data units to the endecryption units, respectively; and simultaneously processing the input data units at the respective endecryption units. According to the encryption/decryption method, parallel processing is performed to encrypt/decrypt data at higher speed.
摘要翻译：包括支持具有调整和密文流传输（XTS）的XES模式的多个边界处理单元的加密/解密方法包括：将输入数据流划分成连续的数据单元; 将分割的数据单元分别输入到内部加密单元; 并且在相应的内部加密单元处同时处理输入数据单元。根据加密/解密方法，并行处理以较高的速度加密/解密数据。

6. 发明申请

US20110129085A1 CRYPTOGRAPHIC DEVICE FOR IMPLEMENTING S-BOX 有权
标题翻译：用于实施S盒的拼接装置
公开(公告)号：US20110129085A1
公开(公告)日：2011-06-02
申请号：US12889854
申请日：2010-09-24
申请人： Hong-Mook Choi , Xingguang Feng
发明人： Hong-Mook Choi , Xingguang Feng
IPC分类号： H04L9/28
CPC分类号： H04L9/00 , H04L9/003 , H04L9/0625 , H04L2209/12 , H04L2209/122 , H04L2209/127
摘要： Provided is a cryptographic device implementing an S-Box of an encryption algorithm using a many-to-one binary function. The cryptographic device includes: arrays of first logic gates including I first logic gates which each receive 2 bits of an input signal; 2N second logic gates which each receive corresponding J bits from among I bits output from the arrays of the first logic gates; and L third logic gates which each receive K bits from among 2N bits output from the second logic gates, wherein there is a many-to-one correspondence between the N bits of the input signal and the K bits input to each of the third logic gates, and wherein the N, I, J, K, and L are positive integers. Because a signal output from each array includes only one active bit, current is always consumed constantly to prevent internal data from leaking out to a hacker.
摘要翻译：提供了一种使用多对一二进制功能实现加密算法的S-Box的加密设备。密码装置包括：第一逻辑门阵列，包括I个第一逻辑门，每个第一逻辑门接收输入信号的2位; 2N个第二逻辑门，每个第二逻辑门从从第一逻辑门的阵列输出的I位中接收相应的J位; 和L个第三逻辑门，每个逻辑门从第二逻辑门输出的2N位中接收K位，其中在输入信号的N位和输入到每个第三逻辑的K位之间存在多对一的对应关系门，并且其中N，I，J，K和L是正整数。因为每个阵列的信号输出仅包含一个有效位，所以电流始终被消耗，以防止内部数据泄漏到黑客中。

7. 发明授权

US08750497B2 Cryptographic device for implementing S-box 有权
标题翻译：用于实现S盒的加密设备
公开(公告)号：US08750497B2
公开(公告)日：2014-06-10
申请号：US12889854
申请日：2010-09-24
申请人： Hong-Mook Choi , Xingguang Feng
发明人： Hong-Mook Choi , Xingguang Feng
IPC分类号： H04K1/00 , H04L9/00
CPC分类号： H04L9/00 , H04L9/003 , H04L9/0625 , H04L2209/12 , H04L2209/122 , H04L2209/127
摘要： Provided is a cryptographic device implementing an S-Box of an encryption algorithm using a many-to-one binary function. The cryptographic device includes: arrays of first logic gates including I first logic gates which each receive 2 bits of an input signal; 2N second logic gates which each receive corresponding J bits from among I bits output from the arrays of the first logic gates; and L third logic gates which each receive K bits from among 2N bits output from the second logic gates, wherein there is a many-to-one correspondence between the N bits of the input signal and the K bits input to each of the third logic gates, and wherein the N, I, J, K, and L are positive integers. Because a signal output from each array includes only one active bit, current is always consumed constantly to prevent internal data from leaking out to a hacker.
摘要翻译：提供了一种使用多对一二进制功能实现加密算法的S-Box的加密设备。密码装置包括：第一逻辑门阵列，包括I个第一逻辑门，每个第一逻辑门接收输入信号的2位; 2N个第二逻辑门，每个第二逻辑门从从第一逻辑门的阵列输出的I位中接收相应的J位; 和L个第三逻辑门，每个逻辑门从第二逻辑门输出的2N位中接收K位，其中在输入信号的N位和输入到每个第三逻辑的K位之间存在多对一的对应关系门，并且其中N，I，J，K和L是正整数。因为每个阵列的信号输出仅包含一个有效位，所以电流始终被消耗，以防止内部数据泄漏到黑客中。

8. 发明授权

US08666064B2 Endecryptor capable of performing parallel processing and encryption/decryption method thereof 有权
标题翻译：能够执行并行处理和加密/解密方法的封装技术
公开(公告)号：US08666064B2
公开(公告)日：2014-03-04
申请号：US12874799
申请日：2010-09-02
申请人： Hong-Mook Choi , Jisoo Kim , Xingguang Feng , Woo-Hyun Lee
发明人： Hong-Mook Choi , Jisoo Kim , Xingguang Feng , Woo-Hyun Lee
IPC分类号： H04L9/00 , H04L9/28 , H04L9/32 , H04K1/04 , H04K1/00
CPC分类号： H04L9/0637 , H04L2209/125 , H04L2209/20
摘要： An encryption/decryption method of an endecryptor including a plurality of endecryption units supporting an XES mode with tweak and ciphertext streaming (XTS) includes dividing an input data stream into consecutive data units; inputting the divided data units to the endecryption units, respectively; and simultaneously processing the input data units at the respective endecryption units. According to the encryption/decryption method, parallel processing is performed to encrypt/decrypt data at higher speed.
摘要翻译：包括支持具有调整和密文流传输（XTS）的XES模式的多个边界处理单元的加密/解密方法包括：将输入数据流划分成连续的数据单元; 将分割的数据单元分别输入到内部加密单元; 并且在相应的内部加密单元处同时处理输入数据单元。根据加密/解密方法，并行处理以较高的速度加密/解密数据。

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