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1. 发明授权

US07167118B1 Centered-pulse consecutive edge modulation (CEM) method and apparatus 有权
标题翻译：中心脉冲连续边缘调制（CEM）方法和装置
公开(公告)号：US07167118B1
公开(公告)日：2007-01-23
申请号：US11297016
申请日：2005-12-08
申请人： John L. Melanson , Melvin L. Hagge , Brian David Trotter
发明人： John L. Melanson , Melvin L. Hagge , Brian David Trotter
IPC分类号： H03M3/00
CPC分类号： H03M3/506 , H03M7/3026 , H03M7/3037
摘要： A centered-pulse consecutive edge modulation (CEM) method and apparatus provides a pulse output that advantageously exploits the full edge update rate of the CEM while providing substantially centered pulses. The method and apparatus also operate without substantial delay in the input control path. The apparatus includes a delta-sigma noise shaping modulator followed by a CEM that receives an output of the delta-sigma modulator quantizer. A non-linear correction signal is applied with polarity alternating at each edge and is applied to the quantizer input or is designed into the quantizer transfer function. The non-linear correction signal compensates for the noise-shaping modulator output such that the expected rising edge and falling edge widths of the CEM output pulses are substantially equal with respect to a DC input to the delta-sigma modulator.
摘要翻译：中心脉冲连续边缘调制（CEM）方法和装置提供脉冲输出，其有利地利用CEM的全边缘更新速率，同时提供基本上居中的脉冲。该方法和装置也在输入控制路径中没有实质延迟的情况下工作。该装置包括后跟有CEM的Δ-Σ噪声整形调制器，其接收Δ-Σ调制器量化器的输出。在每个边缘处以极性交替施加非线性校正信号，并施加到量化器输入或被设计成量化器传递函数。非线性校正信号补偿噪声整形调制器输出，使得CEM输出脉冲的预期上升沿和下降沿宽度相对于Δ-Σ调制器的DC输入基本相等。

2. 发明授权

US06690240B2 Low-jitter loop filter for a phase-locked loop system 有权
标题翻译：用于锁相环系统的低抖动环路滤波器
公开(公告)号：US06690240B2
公开(公告)日：2004-02-10
申请号：US10043558
申请日：2002-01-10
申请人： Adrian Maxim , Baker Scott, III , Edmund M. Schneider , Melvin L. Hagge
发明人： Adrian Maxim , Baker Scott, III , Edmund M. Schneider , Melvin L. Hagge
IPC分类号： H03L700
CPC分类号： H03L7/0893 , H03L7/093 , H03L7/18
摘要： A loop filter device and method for implementing a loop filter for a phase locked loop (“PLL”) circuit, which locks a frequency of a signal to a reference frequency, are disclosed. The loop filter includes a proportional path circuit and an integral path circuit. The proportional path circuit receives a charge pump output and determines and holds a charge to be directed to or taken from a PLL circuit throughout an update period based on a detected phase difference for the update period for locking a frequency of a signal for a PLL circuit to a reference frequency. The integral path circuit is coupled to the proportional path circuit, and the integral path circuit receives another charge pump output and tracks a total charge level for the PLL circuit based on phase differences for present and prior update periods.
摘要翻译：公开了一种用于实现将信号的频率锁定到参考频率的锁相环（“PLL”）电路的环路滤波器的环路滤波器装置和方法。环路滤波器包括比例路径电路和积分路径电路。比例路径电路接收电荷泵输出，并且基于用于锁定PLL电路的信号的频率的更新周期的检测到的相位差来确定并保持在整个更新周期期间被引导到PLL电路或从PLL电路获取的电荷到参考频率。积分路径电路耦合到比例路径电路，并且积分路径电路接收另一个电荷泵输出，并且基于当前和先前更新周期的相位差来跟踪PLL电路的总电荷电平。

3. 发明授权

US07308027B1 Circuits and methods for reducing distortion and noise in pulse width modulation systems utilizing full-bridge drivers 有权
标题翻译：利用全桥驱动器减小脉冲宽度调制系统中的失真和噪声的电路和方法
公开(公告)号：US07308027B1
公开(公告)日：2007-12-11
申请号：US10828816
申请日：2004-04-21
申请人： Johann Guy Gaboriau , Melvin L. Hagge , Lingli Zhang , John Laurence Melanson
发明人： Johann Guy Gaboriau , Melvin L. Hagge , Lingli Zhang , John Laurence Melanson
IPC分类号： H03K7/08
CPC分类号： H03F3/2173 , H03F1/26 , H03F1/32 , H03F3/68 , H03F2200/03 , H03F2200/351 , H03F2200/372
摘要： A pulse width modulation circuit for driving a full-bridge output load includes a pulse width modulation stage for generating, from an input data stream, a pulse width modulated data stream for driving a terminal of a full-bridge output load and another pulse width modulated data stream for driving another terminal of the full bridge output load. A delay circuit delays the another pulse width modulated data stream relative to the pulse width modulated data stream such that edges of the another pulse width modulated data stream and edges of the pulse width modulated data stream are temporally spaced.
摘要翻译：用于驱动全桥输出负载的脉宽调制电路包括脉冲宽度调制级，用于从输入数据流生成用于驱动全桥输出负载的端子的脉冲宽度调制数据流，以及用于驱动全桥输出负载的另一个脉宽调制用于驱动全桥输出负载的另一终端的数据流。延迟电路相对于脉宽调制数据流延迟另一个脉冲宽度调制数据流，使得另一脉宽调制数据流的边缘和脉宽调制数据流的边沿在时间上间隔开。

4. 发明授权

US07706438B1 Circuits and methods for reducing noise and distortion in pulse width modulation systems 有权
标题翻译：用于降低脉冲宽度调制系统噪声和失真的电路和方法
公开(公告)号：US07706438B1
公开(公告)日：2010-04-27
申请号：US10767906
申请日：2004-01-29
申请人： Johann Guy Gaboriau , John Laurence Melanson , Lingli Zhang , Melvin L. Hagge
发明人： Johann Guy Gaboriau , John Laurence Melanson , Lingli Zhang , Melvin L. Hagge
IPC分类号： H03K7/08 , H03M5/08
CPC分类号： H03K7/08 , H03F3/2173
摘要： A pulse width modulation system including a pulse width modulation stage for generating a pulse width modulated signal in response to an input signal and an other pulse width modulation stage for generating an other pulse width modulated signal in response to an other input signal. Additional circuitry ensures that transitions of the pulse width modulated signal and the other pulse width modulated signal are spaced in time by a selected amount for small levels of the input signal.
摘要翻译：一种脉冲宽度调制系统，包括响应于输入信号产生脉宽调制信号的脉冲宽度调制级和用于响应于另一输入信号产生另一脉冲宽度调制信号的其它脉宽调制级。附加电路确保了脉冲宽度调制信号和另一个脉冲宽度调制信号的转换在输入信号的小电平上被时间间隔一定数量。

5. 发明授权

US06828864B2 Low-jitter loop filter for a phase-locked loop system 有权
公开(公告)号：US06828864B2
公开(公告)日：2004-12-07
申请号：US10612200
申请日：2003-07-03
申请人： Adrian Maxim , Baker Scott, III , Edmund M. Schneider , Melvin L. Hagge
发明人： Adrian Maxim , Baker Scott, III , Edmund M. Schneider , Melvin L. Hagge
IPC分类号： H03L700
CPC分类号： H03L7/0893 , H03L7/093 , H03L7/18
摘要： A loop filter device and method for implementing a loop filter for a phase locked loop (“PLL”) circuit, which locks a frequency of a signal to a reference frequency, are disclosed. The loop filter includes a proportional path circuit and an integral path circuit. The proportional path circuit receives a charge pump output and determines and holds a charge to be directed to or taken from a PLL circuit throughout an update period based on a detected phase difference for the update period for locking a frequency of a signal for a PLL circuit to a reference frequency. The integral path circuit is coupled to the proportional path circuit, and the integral path circuit receives another charge pump output and tracks a total charge level for the PLL circuit based on phase differences for present and prior update periods.

6. 发明授权

US4501978A Level shift interface circuit 失效
标题翻译：电平移位接口电路
公开(公告)号：US4501978A
公开(公告)日：1985-02-26
申请号：US444459
申请日：1982-11-24
申请人： Carmine J. Gentile , Melvin L. Hagge , Robert C. Croes
发明人： Carmine J. Gentile , Melvin L. Hagge , Robert C. Croes
IPC分类号： H03K19/0185 , H03K19/017 , H03K19/0175 , H03K19/0944 , H03K19/092 , H03K19/094
CPC分类号： H03K19/09448 , H03K19/01721 , H03K19/017518
摘要： A voltage dropping element is connected in series with the conduction paths of first and second IGFETs, of complementary conductivity, between first and second terminals coupled to first (e.g. 5 volts) and second (e.g. 0 volt) voltage levels, respectively. The gates of the IGFETs are connected to an input terminal to which is applied TTL level signals (e.g. 0.4 to 2.4 volts) and their drains are connected to an output node. When the "high" TTL level (e.g. 2.4 volt) is present, the voltage dropping element reduces the effective gate-to-source voltage (V.sub.GS) of the first IGFET, reducing its conductivity, increasing its effective impedance substantially, and enabling the second IGFET to drive the output node to the second voltage level with little power dissipation. When the "low" TTL input (e.g. 0.4 volt) is present, the second IGFET is turned-off while the first IGFET is turned-on, driving the output node to the voltage at the first power terminal less the voltage drop of the voltage dropping element. A regenerative latch circuit connected to the output node senses the turn-on of the first IGFET and couples the output node to the voltage at the first power terminal eliminating the voltage offset at the output node due to the voltage dropping element.
摘要翻译：分压元件与分别耦合到第一（例如5伏）和第二（例如0伏）电压电平的第一和第二端子之间的互补电导率的第一和第二IGFET的导电路径串联连接。 IGFET的栅极连接到施加有TTL电平信号（例如0.4至2.4伏特）并且其漏极连接到输出节点的输入端子。当存在“高”TTL电平（例如2.4伏特）时，降压元件降低第一IGFET的有效栅极 - 源极电压（VGS），降低其导电性，基本上增加其有效阻抗，并使得第二 IGFET将输出节点驱动到具有很小功耗的第二电压电平。当存在“低”TTL输入（例如0.4伏特）时，第二IGFET在第一IGFET导通时关断，将输出节点驱动到第一电源端子处的电压，减去电压的电压降掉落元素连接到输出节点的再生锁存电路感测第一IGFET的导通，并将输出节点耦合到第一电源端的电压，消除由于降压元件而导致的输出节点处的电压偏移。

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