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1. 发明授权

US5548782A Apparatus for preventing transferring of data with peripheral device for period of time in response to connection or disconnection of the device with the apparatus 失效
标题翻译：用于响应于设备与设备的连接或断开而在一段时间内防止与外围设备传输数据的设备
公开(公告)号：US5548782A
公开(公告)日：1996-08-20
申请号：US58397
申请日：1993-05-07
申请人： Martin S. Michael , Frederick K. Leung
发明人： Martin S. Michael , Frederick K. Leung
IPC分类号： G06F13/14 , G06F1/00 , G06F9/445 , G06F13/40 , G06F15/177 , G06F15/02
CPC分类号： G06F9/4411 , G06F13/4068 , G06F15/177 , G06F2213/0004
摘要： A computer system includes a peripheral device connector interface that automatically identifies the type of peripheral device, if any, coupled to the interface and configures itself for handling data flows to and from peripheral devices of the identified type. The system includes a connector that receives a number of peripheral identification signals that are generated by a peripheral device attached to the connector. Peripheral device data signals, which are also received at the connector, are routed by a connector interface. A number of interface circuits are provided to control the different types of peripheral devices that may be attached to the connector. The interface circuits are coupled to configuration registers that provide operational information for the interface circuits. A transition detector identifies any change in the peripheral identification signals. Any change in the peripheral identification signals corresponds to a change in the peripheral device attached to the connector. In response to a changed peripheral device, an interface disable generator applies a disable signal to the connector interface. A signal decoder is then used to decode the peripheral identification signals so as to identify the peripheral attached to the connector. After the peripheral is identified, configuration data for the peripheral is loaded into the configuration registers.
摘要翻译：计算机系统包括外围设备连接器接口，其自动识别耦合到接口的外围设备的类型（如果有的话），并且配置自身以处理来自所识别类型的外围设备的数据流。该系统包括连接器，其接收由附接到连接器的外围设备产生的多个外围识别信号。在连接器处也接收的外围设备数据信号由连接器接口路由。提供多个接口电路来控制可连接到连接器的不同类型的外围设备。接口电路耦合到为接口电路提供操作信息的配置寄存器。转换检测器识别外围识别信号的任何变化。外围识别信号的任何改变对应于连接到连接器的外围设备的变化。响应于改变的外围设备，接口禁用发生器向连接器接口施加禁用信号。然后使用信号解码器来解码外围识别信号，以便识别连接到连接器的外围设备。识别外设后，外设的配置数据将被加载到配置寄存器中。

2. 发明授权

US5287458A Buffered asynchronous communications elements with receive/transmit control and status reporting 失效
标题翻译：具有接收/发送控制和状态报告的缓冲异步通信元件
公开(公告)号：US5287458A
公开(公告)日：1994-02-15
申请号：US38713
申请日：1993-03-26
申请人： Martin S. Michael , Prashant A. Kanhere , Richard P. Burnley , Franco Iacobelli , Ta-Wei Chien
发明人： Martin S. Michael , Prashant A. Kanhere , Richard P. Burnley , Franco Iacobelli , Ta-Wei Chien
IPC分类号： H04L25/45 , G06F13/12
CPC分类号： H04L25/45
摘要： An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead. The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communication station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times. A receiver time delay interrupt indicates to the CPU that there are data characters in the receiver FIFO which have not reached the programmable trigger level, but which exceed specified time limit conditions. The receiver and transmitter FIFOs may be both individually and simultaneously disabled; a single-bit register flag indicates their status.
摘要翻译：用户可选择的FIFO作为发送器和接收器缓冲器，以减少CPU中断开销。异步通信元件包括从通信站接收串行数据传输的接收器移位寄存器，从接收器移位寄存器接收到用于传送到CPU的并行数据传输的接收器FIFO，从CPU接收并行数据传输的发送器FIFO，以及发射机移位寄存器，其从发射机FIFO接收并行数据传输，用于串行传输到通信站。发送器时间延迟消除了已向CPU指示的发送器FIFO“空”状态的多个中断。接收器FIFO上的可编程中断电平以及继续填充超过编程中断电平的接收器FIFO允许调整可变CPU延迟时间。接收机延时中断向CPU指示接收机FIFO中没有达到可编程触发电平但超过规定时限的数据字符。接收器和发送器FIFO可以单独地并且同时禁用; 单位寄存器标志表示其状态。

3. 发明授权

US5241660A Buffered asynchronous communications element with receive/transmit control and status reporting 失效
标题翻译：具有接收/发送控制和状态报告的缓冲异步通信元件
公开(公告)号：US5241660A
公开(公告)日：1993-08-31
申请号：US703572
申请日：1991-05-17
申请人： Martin S. Michael , Prashant A. Kanhere , Richard P. Burnley , Franco Iacobelli , Ta-Wei Chien
发明人： Martin S. Michael , Prashant A. Kanhere , Richard P. Burnley , Franco Iacobelli , Ta-Wei Chien
IPC分类号： H04L25/45
CPC分类号： H04L25/45
摘要： An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead. The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communication station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times. A receiver time delay interrupt indicates to the CPU that there are data characters in the receiver FIFO which have not reached the programmable trigger level, but which exceed specified time limit conditions. The receiver and transmitter FIFOs may be both individually and simultaneously disabled; a single-bit register flag indicates their status.
摘要翻译：用户可选择的FIFO作为发送器和接收器缓冲器，以减少CPU中断开销。异步通信元件包括从通信站接收串行数据传输的接收器移位寄存器，从接收器移位寄存器接收到用于传送到CPU的并行数据传输的接收器FIFO，从CPU接收并行数据传输的发送器FIFO，以及发射机移位寄存器，其从发射机FIFO接收并行数据传输，用于串行传输到通信站。发送器时间延迟消除了已向CPU指示的发送器FIFO“空”状态的多个中断。接收器FIFO上的可编程中断电平以及继续填充超过编程中断电平的接收器FIFO允许调整可变CPU延迟时间。接收机延时中断向CPU指示接收机FIFO中没有达到可编程触发电平但超过规定时限的数据字符。接收器和发送器FIFO可以单独地并且同时禁用; 单位寄存器标志表示其状态。

4. 发明授权

US5228130A Multi-channel peripheral interface using selectively flaggable channel register sets for concurrent write in response to any selected channel register write instruction 失效
标题翻译：多通道外围接口使用选择性地标记通道寄存器组，以响应任何所选择的通道寄存器写指令进行并行写操作
公开(公告)号：US5228130A
公开(公告)日：1993-07-13
申请号：US809759
申请日：1991-12-18
申请人： Martin S. Michael
发明人： Martin S. Michael
IPC分类号： G06F13/28 , G06F13/38
CPC分类号： G06F13/38 , G06F13/28
摘要： Each of the identical register sets associated with each of the multiple channels of a peripheral device includes an initialization register. Setting the appropriate bit in the initialization register of any one of the channels allows the data processing system serviced by the peripheral device to perform a concurrent write operation to the same selected register in each channel enabled for a concurrent write. The concurrent write operation is based on a standard write instruction and a standard system address.
摘要翻译：与外围设备的多个通道中的每一个相关联的每个相同的寄存器组包括初始化寄存器。设置任何一个通道的初始化寄存器中的适当位允许由外围设备服务的数据处理系统对同时写入的每个通道中的同一个选定寄存器执行并发写操作。并发写入操作基于标准写入指令和标准系统地址。

5. 发明授权

US4823312A Asynchronous communications element 失效
标题翻译：异步通信元件
公开(公告)号：US4823312A
公开(公告)日：1989-04-18
申请号：US924797
申请日：1986-10-30
申请人： Martin S. Michael , Prashant A. Kanhere , Richard P. Burnley , Franco Iacobelli , Ta-Wei Chien
发明人： Martin S. Michael , Prashant A. Kanhere , Richard P. Burnley , Franco Iacobelli , Ta-Wei Chien
IPC分类号： H04L25/45 , H04Q9/00 , G06F3/04 , H04L25/38
CPC分类号： H04L25/45
摘要： An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead.The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communications station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times. A receiver time delay interrupt indicates to the CPU that there are data characters in the receiver FIFO which have not reached the programmable trigger level, but which exceed specified time limit conditions. The receiver and transmitter FIFOs may be both individually and simultaneously disabled; a single-bit register flag indicates their status.
摘要翻译：用户可选择的FIFO作为发送器和接收器缓冲器，以减少CPU中断开销。异步通信元件包括从通信站接收串行数据传输的接收器移位寄存器，从接收器移位寄存器接收到用于传送到CPU的并行数据传输的接收器FIFO，从CPU接收并行数据传输的发送器FIFO，以及发射机移位寄存器，其从发射机FIFO接收并行数据传输，用于串行传输到通信站。发送器时间延迟消除了已向CPU指示的发送器FIFO“空”状态的多个中断。接收器FIFO上的可编程中断电平以及继续填充超过编程中断电平的接收器FIFO允许调整可变CPU延迟时间。接收机延时中断向CPU指示接收机FIFO中没有达到可编程触发电平但超过规定时限的数据字符。接收器和发送器FIFO可以单独地并且同时禁用; 单位寄存器标志表示其状态。

6. 发明授权

US5754764A Combination of input output circuitry and local area network systems 失效
标题翻译：输入输出电路和局域网系统的组合
公开(公告)号：US5754764A
公开(公告)日：1998-05-19
申请号：US200097
申请日：1994-02-22
申请人： Timothy D. Davis , Roman Baker , Dan E. Daugherty , Martin S. Michael , Ahmed Masood , Kent Bruce Waterson , Hon C. Fung , Mark Douglas Koether , J. Scott Johnson
发明人： Timothy D. Davis , Roman Baker , Dan E. Daugherty , Martin S. Michael , Ahmed Masood , Kent Bruce Waterson , Hon C. Fung , Mark Douglas Koether , J. Scott Johnson
IPC分类号： G06F13/38 , H04L7/10 , H04L12/28 , G06F13/00 , H04L12/00
CPC分类号： G06F13/385 , H04L12/28 , H04L7/10
摘要： Input/output and local area network functions are combined into a single integrated circuit on a single semiconductor (e.g., a single piece of silicon). Preferred system embodiments on a single integrated circuit are typically placed inside a host system (e.g., a personal computer based on Intel.RTM.'s 286, 386, 486, and Pentium microprocessors) and interrelate with standard operating systems (e.g., Microsoft.RTM.'s DOS, IBM.RTM.'s OS/2) on traditional, commonly used bus architectures (e.g., Industry Standard Architecture and Enhanced Industry Standard). Local area network circuitry and input and output circuitry are both coupled to at least one host system (and indirectly to potentially any number of host systems tied together via the local area network system) via a common data bus. The input and output circuitry couples the host system to at least one input/output channels. Examples of the types of input/output channels are a first serial interface, a second serial interface, a parallel port, a hard drive, a floppy drive, and/or any combination thereof.
摘要翻译：输入/输出和局域网功能在单个半导体（例如单个硅片）上组合成单个集成电路。单个集成电路上的优选系统实施例通常放置在主机系统（例如，基于Intel TM 286,386,468和Pentium微处理器的个人计算机）内，并与标准操作系统（例如，Microsoft TM DOS，IBM TM的OS / 2）在传统的常用总线架构（例如，行业标准架构和增强行业标准）上。局域网电路和输入和输出电路都经由公共数据总线耦合到至少一个主机系统（并且间接地连接到潜在的任何数量的通过局域网系统连接在一起的主机系统）。输入和输出电路将主机系统耦合到至少一个输入/输出通道。输入/输出通道的类型的示例是第一串行接口，第二串行接口，并行端口，硬盘驱动器，软盘驱动器和/或其任何组合。

7. 发明授权

US5199105A Universal asynchronous receiver/transmitter 失效
标题翻译：通用异步收发器
公开(公告)号：US5199105A
公开(公告)日：1993-03-30
申请号：US745613
申请日：1991-08-15
申请人： Martin S. Michael
发明人： Martin S. Michael
IPC分类号： G06F13/28 , G06F13/38
CPC分类号： G06F13/28 , G06F13/38
摘要： Data characters to be transferred from a peripheral device to a central processing unit are serially shifted into the receiver shift register of a universal asynchronous receiver/transmitter (UART). A multiple byte first-in-first-out memory stores a plurality of data characters received by the shift register. The UART checks the status of each data character stored in the FIFO to determine whether it will trigger an exception, A bytes till exception register indicates the number of data characters remaining in the FIFO until an exception is encountered. Then, upon request by the CPU, the UART provides the count of consecutive valid data characters from the top of the FIFO to the first exception, eliminating the need to check status on every transferred byte. Each of the multiple channels of the UART includes an Initialization Register. Setting the appropriate bit Initialization Register of any UART channel allows concurrent writes to the same selected register in each channel's register set. This function reduces initialization time for all of the common parameters that are loaded into each channel's registers. The UART implements a methodology which allows for the processing of any control characters or errors received by the UART during while internal and/or external FIFOs are being used.
摘要翻译：要从外围设备传输到中央处理单元的数据字符串行地移入通用异步接收器/发送器（UART）的接收器移位寄存器。多字节先进先出存储器存储由移位寄存器接收的多个数据字符。 UART检查存储在FIFO中的每个数据字符的状态，以确定是否触发异常，除非遇到异常，否则A字节直到异常寄存器指示FIFO中剩余的数据字符数。然后，根据CPU的要求，UART提供从FIFO顶部到第一个异常的连续有效数据字符的计数，无需检查每个传输字节的状态。 UART的多个通道中的每一个都包含一个初始化寄存器。设置相应的位任何UART通道的初始化寄存器允许在每个通道的寄存器组中同时写入同一个选定的寄存器。该功能可以减少加载到每个通道寄存器中的所有常见参数的初始化时间。 UART在使用内部和/或外部FIFO时允许处理由UART接收到的任何控制字符或错误的方法。

8. 发明授权

US5140679A Universal asynchronous receiver/transmitter 失效
标题翻译：通用异步接收机/发射机
公开(公告)号：US5140679A
公开(公告)日：1992-08-18
申请号：US244920
申请日：1988-09-14
申请人： Martin S. Michael
发明人： Martin S. Michael
IPC分类号： G06F13/00 , G06F13/28 , G06F13/38
CPC分类号： G06F13/382 , G06F13/28 , G06F13/38 , G06F13/385
摘要： Data characters to be transferred from a peripheral device to a central processing unit are serially shifted into the receiver shift register of a universal asynchronous receiver/transmitter (UART). A multiple byte first-in-first-out memory stores a plurality of data characters received by the shift register. The UART checks the status of each data character stored in the FIFO to determine whether it will trigger an exception. A bytes till exception register indicates the number of data characters remaining in the FIFO until an exception is encountered. Then, upon request by the CPU, the UART provides the count of consecutive valid data characters from the top of the FIFO to the first exception, eliminating the need to check status on every transferred byte. Each of the multiple channels of the UART includes an Initialization Register. Setting the appropriate bit Initializatioin Register of any UART channel allows concurrent writes to the same selected register in each channel's register set. This function reduces initialization time for all of the common parameters that are loaded into each channel's registers. The UART implements a methodology which allows for the processing of any control characters or errors received by the UART during DMA while internal and/or external FIFOs are being used.

9. 发明授权

US5787306A Automatic assignment of I/O addresses in a computer system 失效
标题翻译：在计算机系统中自动分配I / O地址
公开(公告)号：US5787306A
公开(公告)日：1998-07-28
申请号：US245315
申请日：1994-05-18
申请人： Martin S. Michael
发明人： Martin S. Michael
IPC分类号： G06F12/06 , G06F13/42 , G06F12/00
CPC分类号： G06F12/0661 , G06F13/4226
摘要： A peripheral device, connected to an address bus, which has yet to be assigned an I/O address has a pin connected to a configuration select output of a control logic circuit (or a CPU). The peripheral device is reset upon start-up of the system and is not yet required to respond to normal bus accesses or traffic. The CPU analyzes the available addresses in the address space and selects an available I/O address for assignment to that peripheral device. In one embodiment, the CPU then sends a serial bit stream containing the selected I/O address to that peripheral device over a configuration select line. In another embodiment, the CPU asserts a configuration select signal to the peripheral device. The CPU then transmits the selected I/O address to the peripheral device on the address bus. The transmitted I/O address is then stored in the peripheral device, and the device will now respond to this I/O address during subsequent operation of the system. In this way, the peripheral device is assigned an I/O address prior to that device having to interact or become active on the address bus or in the I/O address space.
摘要翻译：连接到地址总线的外围设备尚未被分配I / O地址，其引脚连接到控制逻辑电路（或CPU）的配置选择输出。外围设备在系统启动时复位，并且不需要响应正常总线访问或流量。 CPU分析地址空间中的可用地址，并选择可用的I / O地址以分配给该外围设备。在一个实施例中，CPU然后通过配置选择线将包含所选择的I / O地址的串行比特流发送到该外围设备。在另一实施例中，CPU向外围设备发出配置选择信号。 CPU然后将所选择的I / O地址发送到地址总线上的外围设备。然后将所发送的I / O地址存储在外围设备中，并且设备将在系统的后续操作期间响应该I / O地址。以这种方式，外部设备在该设备必须在地址总线或I / O地址空间中必须交互或变为活动之前被分配I / O地址。

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