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1. 发明授权

US08338815B2 Memory units and related semiconductor devices including nanowires 失效
标题翻译：存储器单元和包括纳米线的相关半导体器件
公开(公告)号：US08338815B2
公开(公告)日：2012-12-25
申请号：US12851268
申请日：2010-08-05
申请人： Moon-Sook Lee , Byeong-Ok Cho , Man-Hyoung Ryoo , Takahiro Yasue
发明人： Moon-Sook Lee , Byeong-Ok Cho , Man-Hyoung Ryoo , Takahiro Yasue
IPC分类号： H01L29/04 , H01L47/00
CPC分类号： H01L27/11507 , B82Y10/00 , H01L27/10 , H01L27/1021 , H01L27/24
摘要： Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes. Related memory units, methods of fabricating semiconductor devices and semiconductor devices are also provided.
摘要翻译：提供了一种制造存储器单元的方法，包括形成多个第一纳米线结构，每个第一纳米线结构包括在第一衬底上沿与第一衬底平行的第一方向延伸的第一纳米线和包围第一纳米线的第一电极层。第一电极层被部分地去除以在第一纳米线下方形成第一电极。填充第一基板上形成有第一纳米线和第一电极的结构之间的空间的第一绝缘层。在第一纳米线和第一绝缘层上形成第二电极层。多个第二纳米线形成在第二电极层上，每个第二纳米线沿垂直于第一方向的第二方向延伸。使用第二纳米线作为蚀刻掩模来部分蚀刻第二电极层以形成多个第二电极。还提供了相关的存储单元，制造半导体器件和半导体器件的方法。

2. 发明申请

US20090189152A1 FERROELECTRIC MEMORY DEVICE 审中-公开
标题翻译：电磁存储器件
公开(公告)号：US20090189152A1
公开(公告)日：2009-07-30
申请号：US12354990
申请日：2009-01-16
申请人： Byeong-Ok Cho , Moon-Sook Lee , Man-Hyoung Ryoo , Jung-Hyeon Kim , Takahiro Yasue
发明人： Byeong-Ok Cho , Moon-Sook Lee , Man-Hyoung Ryoo , Jung-Hyeon Kim , Takahiro Yasue
IPC分类号： H01L51/00 , H01L29/76
CPC分类号： H01L29/78391 , B82Y10/00 , G11C11/22 , H01L29/40111 , H01L29/516 , H01L29/6684
摘要： Provided is a ferroelectric memory device. The ferroelectric memory device includes an inorganic channel pattern on a substrate, a source electrode and a drain electrode spaced apart from each other on the substrate and contacting the inorganic channel pattern, a gate electrode disposed adjacent to the inorganic channel pattern, and an organic ferroelectric layer interposed between the inorganic channel pattern and the gate electrode.
摘要翻译：提供了一种铁电存储器件。铁电存储器件包括在衬底上的无机沟道图案，在衬底上彼此间隔开的源电极和漏电极，并与无机沟道图案接触，邻近无机沟道图案设置的栅电极和有机铁电体介于无机通道图案和栅电极之间的层。

3. 发明申请

US20080113876A1 Probe array and associated methods 审中-公开
标题翻译：探头数组及相关方法
公开(公告)号：US20080113876A1
公开(公告)日：2008-05-15
申请号：US11889455
申请日：2007-08-13
申请人： Won-sun Kim , Sung-min Chi , Jung-hwan Hah , Kyoung-seon Kim , Sang-jun Choi , Man-hyoung Ryoo
发明人： Won-sun Kim , Sung-min Chi , Jung-hwan Hah , Kyoung-seon Kim , Sang-jun Choi , Man-hyoung Ryoo
IPC分类号： C40B30/04 , C40B40/00 , C40B50/18
CPC分类号： C40B40/06 , B01J19/0046 , B01J2219/00432 , B01J2219/00529 , B01J2219/00608 , B01J2219/00621 , B01J2219/00626 , B01J2219/00637 , B01J2219/00659 , B01J2219/00675 , B01J2219/00711 , B01J2219/00722 , B82Y30/00 , C40B30/04 , C40B50/14 , G01N33/54353
摘要： A probe array includes a substrate having at least two projecting features adjacent to one another, each feature including a top surface and a side surface, an isolation region separating the at least two features, at least two active regions, the at least two active regions including the top surfaces of the at least two features, and an inactive region separating the at least two active regions, the inactive region including the isolation region.
摘要翻译：探针阵列包括具有彼此相邻的至少两个突出特征的基底，每个特征包括顶表面和侧表面，隔离区域将至少两个特征区分开，至少两个活性区域，所述至少两个活性区域包括所述至少两个特征的顶表面，以及分离所述至少两个活性区域的非活性区域，所述非活性区域包括所述隔离区域。

4. 发明申请

US20080113300A2 Coating Compositions for Use in Forming Patterns and Methods of Forming Patterns 审中-公开
标题翻译：用于形成图案的涂料组合物和形成图案的方法
公开(公告)号：US20080113300A2
公开(公告)日：2008-05-15
申请号：US11397882
申请日：2006-04-05
申请人： Sang-jun Choi , Mitsuhiro Hata , Man-hyoung Ryoo , Jung-hwan Hah
发明人： Sang-jun Choi , Mitsuhiro Hata , Man-hyoung Ryoo , Jung-hwan Hah
IPC分类号： G03C5/00
CPC分类号： G03F7/40 , H01L21/0273 , H01L21/31144
摘要： A coating composition for forming etch mask patterns may include a polymer and an organic solvent. The polymer may have an aromatic ring substituted by a vinyl ether functional group. The polymer may be, for example, a Novolak resin partially substituted by a vinyl ether functional group or poly(hydroxystyrene) partially substituted by a vinyl ether functional group.
摘要翻译：用于形成蚀刻掩模图案的涂料组合物可以包括聚合物和有机溶剂。聚合物可以具有被乙烯基醚官能团取代的芳环。聚合物可以是例如部分被乙烯基醚官能团取代的酚醛清漆树脂或部分被乙烯基醚官能团取代的聚（羟基苯乙烯）。

5. 发明申请

US20080051298A1 Microarrays including probe cells formed within substrates and methods of making the same 审中-公开
标题翻译：微阵列包括在底物内形成的探针细胞及其制备方法
公开(公告)号：US20080051298A1
公开(公告)日：2008-02-28
申请号：US11891767
申请日：2007-08-13
申请人： Won-sun Kim , Sung-min Chi , Jung-hwan Hah , Kyoung-seon Kim , Sang-jun Choi , Man-hyoung Ryoo
发明人： Won-sun Kim , Sung-min Chi , Jung-hwan Hah , Kyoung-seon Kim , Sang-jun Choi , Man-hyoung Ryoo
IPC分类号： C40B40/04 , C40B50/14
CPC分类号： B82Y30/00 , B01J19/0046 , B01J2219/00317 , B01J2219/00585 , B01J2219/00596 , B01J2219/00605 , B01J2219/00608 , B01J2219/00612 , B01J2219/00621 , B01J2219/00626 , B01J2219/00659 , B01J2219/00662 , B01J2219/00711 , B01J2219/00722
摘要： According to some embodiments of the invention, provided herein is a microarray comprising a substrate; a plurality of probe cells formed in the substrate, wherein at least one probe cell includes a linker; and a probe cell separation area. In addition, in some embodiments, the microarray may include a molecular probe coupled to the linker. Related methods are also described herein.
摘要翻译：根据本发明的一些实施方案，本文提供了包含底物的微阵列; 形成在所述底物中的多个探针单元，其中至少一个探针单元包括接头; 和探针细胞分离区域。此外，在一些实施方案中，微阵列可以包括耦合到接头的分子探针。本文还描述了相关方法。

6. 发明申请

US20050031995A1 Integrated circuit semiconductor device with overlay key and alignment key and method of fabricating the same 有权
标题翻译：具有覆盖键和对准键的集成电路半导体器件及其制造方法
公开(公告)号：US20050031995A1
公开(公告)日：2005-02-10
申请号：US10867468
申请日：2004-06-14
申请人： Chang-Jin Kang , Myeong-Cheol Kim , Man-Hyoung Ryoo , Si-Hyeung Lee , Doo-Youl Lee
发明人： Chang-Jin Kang , Myeong-Cheol Kim , Man-Hyoung Ryoo , Si-Hyeung Lee , Doo-Youl Lee
IPC分类号： G03F9/00 , G03F7/00 , G03F7/20 , H01L21/027 , H01L23/544
CPC分类号： H01L23/544 , G03F7/70633 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.
摘要翻译：一种集成电路半导体器件，包括形成在硅衬底的第一部分中的单元区域，所述单元区域包括形成在所述硅衬底中的第一沟槽，填充在所述第一沟槽中的第一掩埋绝缘层，形成在所述第一沟槽上的第一绝缘图案硅衬底和形成在第一绝缘图案上的第一导电图案。覆盖键区域形成在硅衬底的第二部分中，并且包括在硅衬底中形成的第二沟槽，形成在硅衬底上并用作覆盖键的第二绝缘图案，以及形成在第二衬底上的第二导电图案绝缘图案，并且通过使用第二绝缘图案校正覆盖和对准误差而形成。对准键区域形成在硅衬底的第三部分中，并且包括形成在硅衬底中并用作对准键的第三沟槽，形成在第三沟槽中的第二掩埋绝缘层和形成在第三沟槽上的第三导电图案第二掩埋绝缘层和第三沟槽。

7. 发明申请

US20050012157A1 Semiconductor device having sufficient process margin and method of forming same 有权
标题翻译：具有足够的加工余量的半导体器件及其形成方法
公开(公告)号：US20050012157A1
公开(公告)日：2005-01-20
申请号：US10892588
申请日：2004-07-15
申请人： Man-Hyoung Ryoo , Gi-Sung Yeo , Si-Hyeung Lee , Gyu-Chul Kim , Sung-Gon Jung , Chang-Min Park , Hoo-Sung Cho
发明人： Man-Hyoung Ryoo , Gi-Sung Yeo , Si-Hyeung Lee , Gyu-Chul Kim , Sung-Gon Jung , Chang-Min Park , Hoo-Sung Cho
IPC分类号： G11C11/34 , G11C11/412 , H01L27/02 , H01L27/11
CPC分类号： H01L27/088 , G11C11/412 , H01L27/0203 , H01L27/1104 , Y10S257/903
摘要： According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.
摘要翻译：根据本发明的一些实施例，提供掺杂有P型杂质的衬底。在衬底中掺杂N型杂质以将衬底分成P型杂质区和N型杂质区。在P型和N型杂质区中形成具有第一间距的有源图案。具有第二间距的栅极图案在与有源图案基本垂直的方向上形成在有源图案上。描述和要求保护其他实施例。

8. 发明授权

US08193047B2 Semiconductor device having sufficient process margin and method of forming same 有权
标题翻译：具有足够的加工余量的半导体器件及其形成方法
公开(公告)号：US08193047B2
公开(公告)日：2012-06-05
申请号：US12654798
申请日：2010-01-04
申请人： Man-Hyoung Ryoo , Gi-Sung Yeo , Si-Hyeung Lee , Gyu-Chul Kim , Sung-Gon Jung , Chang-Min Park , Hoo-Sung Cho
发明人： Man-Hyoung Ryoo , Gi-Sung Yeo , Si-Hyeung Lee , Gyu-Chul Kim , Sung-Gon Jung , Chang-Min Park , Hoo-Sung Cho
IPC分类号： H01L21/8239
CPC分类号： H01L27/088 , G11C11/412 , H01L27/0203 , H01L27/1104 , Y10S257/903
摘要： According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.
摘要翻译：根据本发明的一些实施例，提供掺杂有P型杂质的衬底。在衬底中掺杂N型杂质以将衬底分成P型杂质区和N型杂质区。在P型和N型杂质区中形成具有第一间距的有源图案。具有第二间距的栅极图案在与有源图案基本垂直的方向上形成在有源图案上。描述和要求保护其他实施例。

9. 发明授权

US08080886B2 Integrated circuit semiconductor device with overlay key and alignment key and method of fabricating the same 有权
标题翻译：具有覆盖键和对准键的集成电路半导体器件及其制造方法
公开(公告)号：US08080886B2
公开(公告)日：2011-12-20
申请号：US12111651
申请日：2008-04-29
申请人： Chang-Jin Kang , Myeong-Cheol Kim , Man-Hyoung Ryoo , Si-Hyeung Lee , Doo-Youl Lee
发明人： Chang-Jin Kang , Myeong-Cheol Kim , Man-Hyoung Ryoo , Si-Hyeung Lee , Doo-Youl Lee
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , G03F7/70633 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.
摘要翻译：一种集成电路半导体器件，包括形成在硅衬底的第一部分中的单元区域，所述单元区域包括形成在所述硅衬底中的第一沟槽，填充在所述第一沟槽中的第一掩埋绝缘层，形成在所述第一沟槽上的第一绝缘图案硅衬底和形成在第一绝缘图案上的第一导电图案。覆盖键区域形成在硅衬底的第二部分中，并且包括在硅衬底中形成的第二沟槽，形成在硅衬底上并用作覆盖键的第二绝缘图案，以及形成在第二衬底上的第二导电图案绝缘图案，并且通过使用第二绝缘图案校正覆盖和对准误差而形成。对准键区域形成在硅衬底的第三部分中，并且包括形成在硅衬底中并用作对准键的第三沟槽，形成在第三沟槽中的第二掩埋绝缘层和形成在第三沟槽上的第三导电图案第二掩埋绝缘层和第三沟槽。

10. 发明授权

US08034747B2 Photolabile compound, oligomer probe array and substrate for oligomer probe array containing the same, and manufacturing method of the same 失效
标题翻译：不稳定化合物，低聚物探针阵列和含有相同的低聚物探针阵列的底物及其制备方法相同
公开(公告)号：US08034747B2
公开(公告)日：2011-10-11
申请号：US12019843
申请日：2008-01-25
申请人： Sung-min Chi , Jung-hwan Hah , Kyoung-seon Kim , Won-sun Kim , Man-hyoung Ryoo
发明人： Sung-min Chi , Jung-hwan Hah , Kyoung-seon Kim , Won-sun Kim , Man-hyoung Ryoo
IPC分类号： C40B50/14
CPC分类号： C07H19/00 , B01J19/0046 , B01J2219/00432 , B01J2219/00527 , B01J2219/00596 , B01J2219/00608 , B01J2219/00621 , B01J2219/00626 , B01J2219/00711 , B01J2219/00722 , B82Y30/00 , C07D215/14 , C07F9/2408 , C07F9/60 , C07F9/65515 , C07H21/00 , C40B50/14 , Y02P20/55 , Y10T436/143333
摘要： A photolabile compound, an oligomer probe array, and a substrate for oligomer probe array comprising the same, and a manufacturing method of the same are disclosed.
摘要翻译：公开了一种光不稳定化合物，低聚物探针阵列和包含其的低聚物探针阵列用基板及其制造方法。

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