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    • 3. 发明授权
    • Nonvolatile semiconductor memory
    • 非易失性半导体存储器
    • US08223543B2
    • 2012-07-17
    • US13193968
    • 2011-07-29
    • Makoto IwaiHiroshi Nakamura
    • Makoto IwaiHiroshi Nakamura
    • G11C16/04
    • G11C16/3459G11C11/56G11C11/5628G11C11/5635G11C11/5642G11C16/0483G11C16/06G11C16/08G11C16/26G11C16/3436G11C16/3454
    • A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.
    • 存储器包括第一和第二选择栅极晶体管,存储器单元,源极线,位线,连接到作为验证读取的目标的所选存储单元的选定字线,连接的未选择字线 到除所选存储单元之外的未选择的存储单元,用于产生提供给所选择的字线的所选择的读取电位并产生大于所选择的读取电位的未被选择的读取电位的电位产生电路, 以及控制电路,其通过验证被选择的存储器单元的单元电流属于两个值隔离的三个区域中的哪个区域属于三个组中的一个,将选择的存储单元的阈值电压分类为三个组中的一个 当所选择的读取电位为第一值时。
    • 5. 发明申请
    • NONVOLATILE SEMICONDUCTOR MEMORY, METHOD FOR READING OUT THEREOF, AND MEMORY CARD
    • 非易失性半导体存储器,其读出方法和存储卡
    • US20110299339A1
    • 2011-12-08
    • US13210431
    • 2011-08-16
    • Makoto IwaiYoshihisa Watanabe
    • Makoto IwaiYoshihisa Watanabe
    • G11C16/26
    • G11C16/0483G11C11/5642G11C16/26
    • A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory.
    • 非易失性半导体存储器包括:存储单元单元,包括具有电荷累积层和控制电极的多个存储单元,所述存储单元串联电连接; 多个字线,其各自电连接到所述多个存储单元的所述控制电极; 在所述存储单元单元的一端电连接到所述存储单元的源极线; 在所述存储单元单元的另一端电连接到所述存储单元的位线; 以及控制信号生成电路,其在数据读出操作期间,从连接到未选择的存储器的未选择的字线的选择时刻开始,选择连接到所述存储单元的所述存储单元的字线的定时。
    • 6. 发明申请
    • NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    • 非易失性半导体存储器件
    • US20110242902A1
    • 2011-10-06
    • US13073365
    • 2011-03-28
    • Makoto IWAI
    • Makoto IWAI
    • G11C16/10
    • G11C16/0483G11C16/10G11C16/3418
    • A nonvolatile semiconductor memory device includes: a memory cell array including a plurality of memory cells; a plurality of word lines each connected in common to memory cells arranged in a corresponding one of rows among the plurality of memory cells; a voltage generator including a clock signal cycle controller configured to lengthen a cycle of a clock signal every time writing is performed at a stepped-up program voltage to the memory cells connected to a word line selected from the word lines, the voltage generator being configured to generate a desired output voltage by using the clock signal, wherein the clock signal cycle controller performs control in such a way that a ramp up rate for writing at the stepped-up program voltage is kept substantially equal to a ramp up rate for writing at an initial program voltage.
    • 非易失性半导体存储器件包括:包括多个存储单元的存储单元阵列; 多个字线,其共同地连接到布置在所述多个存储器单元中的相应行中的存储器单元; 电压发生器,包括时钟信号周期控制器,其被配置为每当以升压编程电压执行写入时延长时钟信号的周期,连接到从字线选择的字线连接的存储单元,所述电压发生器被配置 通过使用时钟信号产生期望的输出电压,其中时钟信号周期控制器以这样一种方式进行控制,使得以升压编程电压写入的斜升速率保持基本上等于用于写入的上升速率 初始编程电压。
    • 7. 发明申请
    • SEMICONDUCTOR STORAGE DEVICE AND READING METHOD THEREOF
    • 半导体存储器件及其读取方法
    • US20110176366A1
    • 2011-07-21
    • US12978878
    • 2010-12-27
    • Rieko TANAKAMakoto Iwai
    • Rieko TANAKAMakoto Iwai
    • G11C16/04G11C16/26
    • G11C16/0408G11C16/26
    • An embodiment of the invention provides a semiconductor storage device including a NAND string, a SEN node, and a capacitor. The NAND string includes plural series-connected memory cells, and one end of the NAND string is connected to a bit line while the other end is connected to a common source line. The SEN node is configured to be able to be electrically connected to a voltage source and the bit line. In the capacitor, one end is connected to the SEN node while the other end is connected to a CLK node to which a voltage within a predetermined range is applied. A discharge rate of the SEN node is enhanced by decreasing a capacitance during discharge of the SEN node only when a selected memory cell selected from the plural memory cells is an on-cell.
    • 本发明的实施例提供一种包括NAND串,SEN节点和电容器的半导体存储装置。 NAND串包括多个串联存储单元,并且NAND串的一端连接到位线,而另一端连接到公共源极线。 SEN节点被配置为能够电连接到电压源和位线。 在电容器中,一端连接到SEN节点,而另一端连接到施加了预定范围内的电压的CLK节点。 只有当从多个存储单元中选择的所选择的存储单元是开小区时,通过减少SEN节点的放电期间的电容来增强SEN节点的放电率。