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1. 发明申请

US20110176366A1 SEMICONDUCTOR STORAGE DEVICE AND READING METHOD THEREOF 有权
标题翻译：半导体存储器件及其读取方法
公开(公告)号：US20110176366A1
公开(公告)日：2011-07-21
申请号：US12978878
申请日：2010-12-27
申请人： Rieko TANAKA , Makoto Iwai
发明人： Rieko TANAKA , Makoto Iwai
IPC分类号： G11C16/04 , G11C16/26
CPC分类号： G11C16/0408 , G11C16/26
摘要： An embodiment of the invention provides a semiconductor storage device including a NAND string, a SEN node, and a capacitor. The NAND string includes plural series-connected memory cells, and one end of the NAND string is connected to a bit line while the other end is connected to a common source line. The SEN node is configured to be able to be electrically connected to a voltage source and the bit line. In the capacitor, one end is connected to the SEN node while the other end is connected to a CLK node to which a voltage within a predetermined range is applied. A discharge rate of the SEN node is enhanced by decreasing a capacitance during discharge of the SEN node only when a selected memory cell selected from the plural memory cells is an on-cell.
摘要翻译：本发明的实施例提供一种包括NAND串，SEN节点和电容器的半导体存储装置。 NAND串包括多个串联存储单元，并且NAND串的一端连接到位线，而另一端连接到公共源极线。 SEN节点被配置为能够电连接到电压源和位线。在电容器中，一端连接到SEN节点，而另一端连接到施加了预定范围内的电压的CLK节点。只有当从多个存储单元中选择的所选择的存储单元是开小区时，通过减少SEN节点的放电期间的电容来增强SEN节点的放电率。

2. 发明申请

US20110063915A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110063915A1
公开(公告)日：2011-03-17
申请号：US12723960
申请日：2010-03-15
申请人： Rieko TANAKA , Takumi Abe
发明人： Rieko TANAKA , Takumi Abe
IPC分类号： G11C16/04 , G11C16/06 , G11C7/00
CPC分类号： G11C16/24 , G11C16/32
摘要： A non-volatile semiconductor memory device includes a memory cell array having a plurality of non-volatile memory cells capable electrically rewriting data, bit lines and source lines. A driver circuit is coupled with the source lines of the memory cell array to output a voltage higher than a power source voltage or a programming voltage for writing data in the memory cell by switching over, and the driver circuit discharges the source lines to ground. A sense amplifier circuit is coupled with the bit line and reads out the data in the memory cell. The sense amplifier includes a sense node and a capacitor having first and second terminals, and the first terminal is coupled with the sense node. The sense node is boosted by a plurality of voltages applied to the second terminal of the capacitor.
摘要翻译：非易失性半导体存储器件包括具有能够电重写数据，位线和源极线的多个非易失性存储单元的存储单元阵列。驱动电路与存储单元阵列的源极线耦合，以输出高于电源电压或编程电压的电压，用于通过切换将数据写入存储单元，并且驱动电路将源极线放电到地。读出放大器电路与位线耦合并读出存储器单元中的数据。感测放大器包括感测节点和具有第一和第二终端的电容器，并且第一端子与感测节点耦合。感测节点被施加到电容器的第二端子的多个电压升压。

3. 发明申请

US20120163095A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20120163095A1
公开(公告)日：2012-06-28
申请号：US13332682
申请日：2011-12-21
申请人： Rieko TANAKA
发明人： Rieko TANAKA
IPC分类号： G11C16/10
CPC分类号： G11C16/3459
摘要： A semiconductor memory device includes a plurality of bit lines connected to memory cells; a sense amplifier connected to the plurality of bit lines; a memory unit configured to hold failure data of the bit lines; and a controller configured to perform control such that if it is judged that there is a failure in a second bit line adjacent to a first bit line selected in writing data on the basis of the failure data for the bit lines, the potential of the second bit line is set to a first potential in at least any one of programming and verification.
摘要翻译：半导体存储器件包括连接到存储器单元的多个位线; 连接到所述多个位线的读出放大器; 存储单元，被配置为保存位线的故障数据; 以及控制器，被配置为执行控制，使得如果根据位线的故障数据判断在写入数据时选择的与第一位线相邻的第二位线中存在故障，则第二位线的电位在编程和验证中的至少任何一个中将位线设置为第一电位。

4. 发明申请

US20110090736A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110090736A1
公开(公告)日：2011-04-21
申请号：US12974065
申请日：2010-12-21
申请人： Rieko TANAKA , Koichi Fukuda , Takumi Abe
发明人： Rieko TANAKA , Koichi Fukuda , Takumi Abe
IPC分类号： G11C16/26 , G11C16/04
CPC分类号： G11C16/26 , G11C16/0483
摘要： A semiconductor memory device includes a sense amplifier which senses identical multilevel data, which is stored in a memory cell, a plurality of number of times at a time of read, and a n-channel MOS transistor which has a current path one end of which is connected to the sense amplifier and the other end of which is connected to a bit line. The device further include a control unit which applies a first voltage to a gate electrode of the n-channel MOS transistor, thereby setting the n-channel MOS transistor in an ON state, and applies a second voltage which is higher than the first voltage, to the gate electrode during a period after first sense and before second sense.
摘要翻译：一种半导体存储器件包括读出放大器，该读出放大器在读取时感测存储在存储器单元中的多个相同的多电平数据，多个次数的n沟道MOS晶体管以及其一端的电流路径连接到读出放大器，另一端连接到位线。该装置还包括控制单元，其向n沟道MOS晶体管的栅电极施加第一电压，从而将n沟道MOS晶体管设置为导通状态，并施加高于第一电压的第二电压，在第一感测之后的时段期间和第二感测之前的栅电极。

5. 发明申请

US20110063922A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110063922A1
公开(公告)日：2011-03-17
申请号：US12875662
申请日：2010-09-03
申请人： Rieko TANAKA , Koichi Fukuda
发明人： Rieko TANAKA , Koichi Fukuda
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/06 , G11C16/32 , G11C16/3418
摘要： Nonvolatile semiconductor memory device according to one embodiment includes: a plurality of planes; a memory cell array provided in the plurality of planes respectively; bit lines; and a control circuit. Each memory cell array is configured as an array of NAND cell units each including a memory string. The memory string includes a plurality of nonvolatile memory cells connected in series. The bit lines are connected to a first end of the NAND cell units, respectively. The control circuit controls a write operation of charging the bit lines up to a certain voltage value, and then setting data in the nonvolatile memory cells to a certain threshold voltage distribution state. The control circuit is configured to be capable of executing an operation of charging the bit lines in a write operation by varying timings of starting charging the bit lines among the plurality of planes.
摘要翻译：根据一个实施例的非易失性半导体存储器件包括：多个平面; 分别设置在所述多个平面中的存储单元阵列; 位线和控制电路。每个存储单元阵列被配置为每个包括存储器串的NAND单元阵列的阵列。存储器串包括串联连接的多个非易失性存储单元。位线分别连接到NAND单元单元的第一端。控制电路控制对位线充电达一定电压值的写入操作，然后将非易失性存储单元中的数据设置到一定的阈值电压分布状态。控制电路被配置为能够通过改变开始对多个平面中的位线充电的定时来执行在写入操作中对位线进行充电的操作。

6. 发明申请

US20090323426A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090323426A1
公开(公告)日：2009-12-31
申请号：US12493680
申请日：2009-06-29
申请人： Rieko TANAKA , Koichi FUKUDA , Takumi ABE
发明人： Rieko TANAKA , Koichi FUKUDA , Takumi ABE
IPC分类号： G11C16/04 , G11C7/10 , H01L29/792
CPC分类号： G11C16/26 , G11C16/0483
摘要： A semiconductor memory device includes a sense amplifier which senses identical multilevel data, which is stored in a memory cell, a plurality of number of times at a time of read, and a n-channel MOS transistor which has a current path one end of which is connected to the sense amplifier and the other end of which is connected to a bit line. The device further include a control unit which applies a first voltage to a gate electrode of the n-channel MOS transistor, thereby setting the n-channel MOS transistor in an ON state, and applies a second voltage which is higher than the first voltage, to the gate electrode during a period after first sense and before second sense.
摘要翻译：半导体存储器件包括读出放大器，该读出放大器在读取时感测存储在存储单元中多个次数的相同的多电平数据，以及具有其一端的电流通路的n沟道MOS晶体管连接到读出放大器，另一端连接到位线。该装置还包括控制单元，其向n沟道MOS晶体管的栅电极施加第一电压，从而将n沟道MOS晶体管设置为导通状态，并施加高于第一电压的第二电压，在第一感测之后的时段期间和第二感测之前的栅电极。

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