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1. 发明授权

US07447071B2 Low voltage column decoder sharing a memory array p-well 有权
标题翻译：共享一个存储阵列p-well的低压列解码器
公开(公告)号：US07447071B2
公开(公告)日：2008-11-04
申请号：US11557627
申请日：2006-11-08
申请人： Massimiliano Frulio , Stefano Surico , Andrea Sacco , Davide Manfre
发明人： Massimiliano Frulio , Stefano Surico , Andrea Sacco , Davide Manfre
IPC分类号： G11C11/34
CPC分类号： G11C16/08
摘要： A plurality of memory sub-arrays are formed in a p-well region. Each of the memory sub-arrays has at least one first-level column decoder that includes a plurality of low-voltage MOS selector transistors that are also formed within the p-well. A last-level decoder is formed outside of the p-well region and includes high-voltage MOS transistors to provide an output signal to one of an array of sense amplifiers. During a memory erase mode of operation, a high voltage is provided to bias the p-well region and a plurality of high-voltage switches are activated to provide a high voltage to gate terminals of the selector transistor in the first-level column decoders. One or more intermediate-level column decoders are formed as low-voltage selector transistors in the p-well between the first-level column decoder and the last-level column decoder. Each of the intermediate-level column decoders also has a high-voltage switch that is activated during a memory erase mode of operation to provide a high voltage to gate terminals of the intermediate-level column decoders.
摘要翻译：多个存储器子阵列形成在p阱区域中。每个存储器子阵列具有至少一个第一级列解码器，其包括也形成在p阱内的多个低压MOS选择晶体管。最后一级解码器形成在p阱区域外部，并且包括高电压MOS晶体管，以向读出放大器阵列之一提供输出信号。在存储器擦除操作模式期间，提供高电压以偏置p阱区域，并且激活多个高压开关以向第一级列解码器中的选择器晶体管的栅极端提供高电压。在第一级列解码器和最后一级列解码器之间的p阱中形成一个或多个中间级列解码器作为低电压选择晶体管。每个中间级列解码器还具有在存储器擦除操作模式期间激活的高压开关，以向中级列解码器的栅极端提供高电压。

2. 发明授权

US07436232B2 Regenerative clock repeater 有权
标题翻译：再生时钟中继器
公开(公告)号：US07436232B2
公开(公告)日：2008-10-14
申请号：US10666142
申请日：2003-09-17
申请人： Stefano Sivero , Massimiliano Frulio
发明人： Stefano Sivero , Massimiliano Frulio
IPC分类号： H03K5/01
CPC分类号： H03K19/01721 , G06F1/10
摘要： A regenerative clock repeater comprises an edge detector and an output driver means to produce the clock signal by recovering its high logical level and low logical level. The output driver means further comprises a pull-up and a pull-down circuitry adapted to receive a pair of control signals. These control signals are generated by the edge detector to sense the rising edge and falling edge of the clock signal. Inside the edge detector, a pair of threshold level detectors detect a high and a low logical level of the clock signal and inputs the results to a combination of logic gates and a latch to keep the locations of the signal markers fixed. These fixed-location of control signals trigger the output driver means to recover the high logical level and the low logical level of said clock signal.
摘要翻译：再生时钟中继器包括边缘检测器和通过恢复其高逻辑电平和低逻辑电平来产生时钟信号的输出驱动器装置。输出驱动器装置还包括适于接收一对控制信号的上拉电路和下拉电路。这些控制信号由边缘检测器产生，以检测时钟信号的上升沿和下降沿。在边缘检测器内部，一对阈值电平检测器检测时钟信号的高逻辑电平和低逻辑电平，并将结果输入逻辑门和锁存器的组合，以保持信号标记的位置固定。控制信号的这些固定位置触发输出驱动器装置来恢复所述时钟信号的高逻辑电平和低逻辑电平。

3. 发明申请

US20080136500A1 CHARGE PUMP FOR GENERATION OF MULTIPLE OUTPUT-VOLTAGE LEVELS 有权
标题翻译：用于产生多个输出电压的充电泵
公开(公告)号：US20080136500A1
公开(公告)日：2008-06-12
申请号：US11608941
申请日：2006-12-11
申请人： Massimiliano Frulio , Stefano Sivero , Marco Passerini , Fabio Tassan Caser
发明人： Massimiliano Frulio , Stefano Sivero , Marco Passerini , Fabio Tassan Caser
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , G11C5/145 , G11C16/30 , H02M2001/007 , H02M2001/009
摘要： A charge pump circuit for generating a plurality of voltages in excess of a supply voltage includes a first group of cascaded charge-pump stages, the input of a first charge pump stage in the first group being driven from the supply voltage. A first output stage has an input driven from the output of a last charge pump stage of the first group and an output coupled to a first voltage node. A second group of cascaded charge-pump stages is provided, the input of the first charge pump stage of the second group being driven from the output of the last charge pump stage of the first group. A second output stage has an input driven from the output of the last charge pump stage in the second group and an output coupled to a second voltage node.
摘要翻译：用于产生超过电源电压的多个电压的电荷泵电路包括第一组级联电荷泵级，第一组中的第一电荷泵级的输入从电源电压驱动。第一输出级具有从第一组的最后电荷泵级的输出驱动的输入和耦合到第一电压节点的输出。提供了第二组级联电荷泵级，第二组的第一电荷泵级的输入从第一组的最后一个电荷泵级的输出驱动。第二输出级具有从第二组中的最后一个电荷泵级的输出驱动的输入和耦合到第二电压节点的输出。

4. 发明申请

US20050073355A1 HIGH PRECISION DIGITAL-TO-ANALOG CONVERTER WITH OPTIMIZED POWER CONSUMPTION 有权
标题翻译：具有优化功耗的高精度数字到模拟转换器
公开(公告)号：US20050073355A1
公开(公告)日：2005-04-07
申请号：US10753273
申请日：2004-01-07
申请人： Stefano Sivero , Lorenzo Bedarida , Massimiliano Frulio
发明人： Stefano Sivero , Lorenzo Bedarida , Massimiliano Frulio
IPC分类号： G05F1/10 , G05F3/02 , H02M20060101 , H02M3/07 , H02M5/42 , H03M1/76
CPC分类号： H02M3/07 , H03M1/765
摘要： A regulated charge pump circuit having two-way switching means that switches between a first feedback pathway that provides a precise and stable voltage output and a second feedback pathway that provides a regulated voltage output with low current consumption from the power source. The first feedback pathway maintains a precise voltage output by regulating a pass device that draws current to the voltage output. The second feedback pathway regulates the voltage output by controlling the connection of a clock input to the charge pump. A variable resistor is used to set the regulated level of the voltage output. A digital-to analog converter is formed by using a combination logic circuit to convert a digital input signal to a control signal for the variable resistor.
摘要翻译：一种具有双向切换装置的调节电荷泵电路，其在提供精确和稳定的电压输出的第一反馈通路与从电源提供具有低电流消耗的调节电压输出的第二反馈通路之间切换。第一反馈通道通过调节将电流吸引到电压输出的通过装置来保持精确的电压输出。第二反馈通道通过控制时钟输入到电荷泵的连接来调节电压输出。可变电阻用于设置电压输出的稳定电平。通过使用组合逻辑电路将数字输入信号转换成可变电阻器的控制信号，形成数模转换器。

5. 发明申请

WO2008085781A1 BIASING CURRENT TO SPEED UP CURRENT MIRROR SETTLING TIME 审中-公开
标题翻译：偏离当前速度以加速当前镜像稳定时间
公开(公告)号：WO2008085781A1
公开(公告)日：2008-07-17
申请号：PCT/US2007/089119
申请日：2007-12-28
申请人： ATMEL CORPORATION , PELLI, Gabriele , LORENZO, Bedarida , MASSIMILIANO, Frulio , BETTINI, Andrea
发明人： PELLI, Gabriele , LORENZO, Bedarida , MASSIMILIANO, Frulio , BETTINI, Andrea
IPC分类号： G05F3/26 , G05F3/00
CPC分类号： H03F3/343 , G09G3/20 , G09G3/3216 , G09G3/3225
摘要： A current mirror circuit includes a first current-mirror transistor coupled to a second current- mirror transistor. A load is coupled to the second current-mirror transistor. A first current source is coupled to the first current-mirror transistor to cause a bias current to flow through the first current-mirror transistor and a second current source is coupled to the second current- mirror transistor and in parallel with the load to shunt the bias current away from the load.
摘要翻译：电流镜像电路包括耦合到第二电流镜像晶体管的第一电流镜像晶体管。负载耦合到第二电流镜晶体管。第一电流源耦合到第一电流镜像晶体管以引起偏置电流流过第一电流镜像晶体管，并且第二电流源耦合到第二电流镜像晶体管并且与负载并联以分流偏离负载的电流。

6. 发明授权

US07579902B2 Charge pump for generation of multiple output-voltage levels 有权
标题翻译：用于产生多个输出电压电平的电荷泵
公开(公告)号：US07579902B2
公开(公告)日：2009-08-25
申请号：US11608941
申请日：2006-12-11
申请人： Massimiliano Frulio , Stefano Sivero , Marco Passerini , Fabio Tassan Caser
发明人： Massimiliano Frulio , Stefano Sivero , Marco Passerini , Fabio Tassan Caser
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , G11C5/145 , G11C16/30 , H02M2001/007 , H02M2001/009
摘要： A charge pump circuit for generating a plurality of voltages in excess of a supply voltage includes a first group of cascaded charge-pump stages, the input of a first charge pump stage in the first group being driven from the supply voltage. A first output stage has an input driven from the output of a last charge pump stage of the first group and an output coupled to a first voltage node. A second group of cascaded charge-pump stages is provided, the input of the first charge pump stage of the second group being driven from the output of the last charge pump stage of the first group. A second output stage has an input driven from the output of the last charge pump stage in the second group and an output coupled to a second voltage node.
摘要翻译：用于产生超过电源电压的多个电压的电荷泵电路包括第一组级联电荷泵级，第一组中的第一电荷泵级的输入从电源电压驱动。第一输出级具有从第一组的最后电荷泵级的输出驱动的输入和耦合到第一电压节点的输出。提供了第二组级联电荷泵级，第二组的第一电荷泵级的输入从第一组的最后一个电荷泵级的输出驱动。第二输出级具有从第二组中的最后一个电荷泵级的输出驱动的输入和耦合到第二电压节点的输出。

7. 发明授权

US07430150B2 Method and system for providing sensing circuitry in a multi-bank memory device 有权
标题翻译：用于在多存储体存储器件中提供感测电路的方法和系统
公开(公告)号：US07430150B2
公开(公告)日：2008-09-30
申请号：US11123544
申请日：2005-05-05
申请人： Massimiliano Frulio , Stefano Sivero , Fabio Tassan Caser , Mauro Chinosi
发明人： Massimiliano Frulio , Stefano Sivero , Fabio Tassan Caser , Mauro Chinosi
IPC分类号： G11C11/34 , G11C16/06 , G11C7/00 , G11C7/02 , G11C7/06
CPC分类号： G11C8/12 , G11C5/025 , G11C7/06 , G11C16/26
摘要： A method and system for providing a multi-bank memory is described. The method and system include providing a plurality of banks. Each of the plurality of banks includes at least one array including a plurality of memory cells and analog sensing circuitry. The method and system further include providing common digital sensing circuitry coupled with the plurality of banks.
摘要翻译：描述了一种用于提供多存储体存储器的方法和系统。该方法和系统包括提供多个银行。多个存储体中的每一个包括包括多个存储单元和模拟感测电路的至少一个阵列。该方法和系统还包括提供与多个存储体耦合的公共数字感测电路。

8. 发明申请

US20080143395A1 METHOD AND DEVICE FOR MANAGING A POWER SUPPLY POWER-ON SEQUENCE 有权
标题翻译：用于管理电源供电序列的方法和设备
公开(公告)号：US20080143395A1
公开(公告)日：2008-06-19
申请号：US11611416
申请日：2006-12-15
申请人： Massimiliano Frulio , Stefano Surico , Andrea Bettini , Monica Marziani
发明人： Massimiliano Frulio , Stefano Surico , Andrea Bettini , Monica Marziani
IPC分类号： H03L7/00
CPC分类号： G11C5/147 , G11C5/143
摘要： Apparatus, systems, and methods are disclosed that operate to trigger a reference voltage generator from a supply voltage detector, compare an output voltage level from the reference voltage generator with the a supply voltage, and to generate an enable signal when the supply voltage is greater than the output voltage level. Additional apparatus, systems, and methods are disclosed.
摘要翻译：公开了用于从电源电压检测器触发参考电压发生器的装置，系统和方法，将来自参考电压发生器的输出电压电平与电源电压进行比较，并且当电源电压较大时产生使能信号比输出电压水平高。公开了附加装置，系统和方法。

9. 发明授权

US07158415B2 System for performing fast testing during flash reference cell setting 有权
标题翻译：在闪存参考单元设置期间执行快速测试的系统
公开(公告)号：US07158415B2
公开(公告)日：2007-01-02
申请号：US11089268
申请日：2005-03-24
申请人： Lorenzo Bedarida , Simone Bartoli , Stefano Surico , Massimiliano Frulio
发明人： Lorenzo Bedarida , Simone Bartoli , Stefano Surico , Massimiliano Frulio
IPC分类号： G11C16/10
CPC分类号： G11C29/028 , G11C16/04 , G11C29/24 , G11C29/50 , G11C29/50004 , G11C2029/5004
摘要： An embedded circuit in a memory device is used in place of an external test device to perform time-consuming tasks such as voltage verification during the setting of reference cells. An external test device programs at least one reference cell to a predetermined value. The embedded circuit uses the cell programmed by the external device as a comparative reference to program additional reference cells.
摘要翻译：使用存储器件中的嵌入式电路来代替外部测试装置来执行耗费时间的任务，例如参考单元设置期间的电压验证。外部测试装置将至少一个参考单元编程为预定值。嵌入式电路使用由外部设备编程的单元作为比较参考来编程附加参考单元。

10. 发明申请

US20060140030A1 System for performing fast testing during flash reference cell setting 有权
标题翻译：在闪存参考单元设置期间执行快速测试的系统
公开(公告)号：US20060140030A1
公开(公告)日：2006-06-29
申请号：US11089268
申请日：2005-03-24
申请人： Lorenzo Bedarida , Simone Bartoli , Stefano Surico , Massimiliano Frulio
发明人： Lorenzo Bedarida , Simone Bartoli , Stefano Surico , Massimiliano Frulio
IPC分类号： G11C29/00
CPC分类号： G11C29/028 , G11C16/04 , G11C29/24 , G11C29/50 , G11C29/50004 , G11C2029/5004
摘要： An embedded circuit in a memory device is used in place of an external test device to perform time-consuming tasks such as voltage verification during the setting of reference cells. An external test device programs at least one reference cell to a predetermined value. The embedded circuit uses the cell programmed by the external device as a comparative reference to program additional reference cells.
摘要翻译：使用存储器件中的嵌入式电路来代替外部测试装置来执行耗费时间的任务，例如参考单元设置期间的电压验证。外部测试装置将至少一个参考单元编程为预定值。嵌入式电路使用由外部设备编程的单元作为比较参考来编程附加参考单元。

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