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1. 发明申请

US20120187927A1 VOLTAGE REGULATION CIRCUITRY AND RELATED OPERATING METHODS 有权
标题翻译：电压调节电路及相关操作方法
公开(公告)号：US20120187927A1
公开(公告)日：2012-07-26
申请号：US13013220
申请日：2011-01-25
申请人： Chuanzhao Yu , Luis J. Briones
发明人： Chuanzhao Yu , Luis J. Briones
IPC分类号： G05F1/595 , G05F1/575
CPC分类号： G05F1/575
摘要： Apparatus for voltage regulation circuits and related operating methods are provided. An exemplary voltage regulation circuit includes a voltage regulation arrangement that provides a regulated output voltage based on an input voltage reference, a phase compensation arrangement coupled to the voltage regulation arrangement and configured to increase a phase margin of the voltage regulation arrangement, and detection circuitry coupled to the phase compensation arrangement. The detection circuitry is configured to disable the phase compensation arrangement in response to detecting an output current that is less than a threshold value.
摘要翻译：提供了用于调压电路和相关操作方法的装置。示例性电压调节电路包括电压调节装置，其基于输入电压基准提供调节的输出电压;耦合到电压调节装置的相位补偿装置，并且被配置为增加电压调节装置的相位裕度，以及耦合的检测电路到相位补偿装置。检测电路被配置为响应于检测到小于阈值的输出电流而禁用相位补偿装置。

2. 发明授权

US07055047B2 Selective implementation of power management schemes based on detected computer operating environment 有权
标题翻译：基于检测到的计算机操作环境选择性实施电源管理方案
公开(公告)号：US07055047B2
公开(公告)日：2006-05-30
申请号：US10410089
申请日：2003-04-09
申请人： Klaas Wortel , David K. Lovelace , Luis J. Briones
发明人： Klaas Wortel , David K. Lovelace , Luis J. Briones
IPC分类号： G06F1/32
CPC分类号： G06F1/3215 , G06F1/3259 , Y02D10/155
摘要： Detecting a radio frequency (RF) environment around a computer and using a power management scheme for an RF user input device being used by the computer system. If the computer system is in a single user environment, a power management scheme may be used to conserve power on the RF user input device. If the computer system is in a multi-user environment, a power management scheme may be used to minimize interference between neighboring computer systems by minimizing the signal strength of the RF signal from the RF user input device and the RF signal from the computer system.
摘要翻译：检测计算机周围的射频（RF）环境，并为计算机系统正在使用的RF用户输入设备使用电源管理方案。如果计算机系统处于单个用户环境中，则可以使用电源管理方案来节省RF用户输入设备上的功率。如果计算机系统处于多用户环境中，则可以使用功率管理方案来最小化来自RF用户输入设备的RF信号的信号强度和来自计算机系统的RF信号来最小化相邻计算机系统之间的干扰。

3. 发明授权

US06900675B2 All digital PLL trimming circuit 有权
标题翻译：所有数字PLL微调电路
公开(公告)号：US06900675B2
公开(公告)日：2005-05-31
申请号：US10653614
申请日：2003-09-02
申请人： Luis J. Briones
发明人： Luis J. Briones
IPC分类号： H03L7/06 , H03L7/087 , H03L7/113 , H03L7/191
CPC分类号： H03L7/113 , H03L7/087 , H03L7/191
摘要： In one set of embodiments, the invention comprises a system and method for automatically trimming the center frequency of a VCO in a PLL. The trimming may be performed by a digitally controlled trimming circuit, which may be operated to modify a gain of the VCO and may be used as part of a clock recovery architecture or as part of a high-end PLL. It may also be used by itself in low-end PLLs. In one embodiment, a second loop based solely on the frequency difference between a reference frequency and a divided output frequency of the VCO is introduced into the PLL loop. This frequency loop may be optimized by the inclusion of a gain control stage, which may lower the locking time. A control module may also be introduced to delay the deployment of the phase detector until the frequency loop has fully converged, that is until trimming has been completed, thus preventing the two loops from interfering with each other and compromising each other's performance.
摘要翻译：在一组实施例中，本发明包括用于在PLL中自动调整VCO的中心频率的系统和方法。可以通过数字控制的微调电路执行修整，该电路可以被操作以修改VCO的增益，并且可以用作时钟恢复架构的一部分或作为高端PLL的一部分。它也可以在低端PLL中自己使用。在一个实施例中，仅基于VCO的参考频率和分频输出频率之间的频率差的第二回路被引入PLL环路。该频率环可以通过包括增益控制级来优化，这可以降低锁定时间。还可以引入控制模块来延迟相位检测器的部署，直到频率回路完全收敛，即直到修整已经完成，从而防止两个回路相互干扰并且彼此的性能相抵消。

4. 发明授权

US08482266B2 Voltage regulation circuitry and related operating methods 有权
标题翻译：电压调节电路及相关操作方法
公开(公告)号：US08482266B2
公开(公告)日：2013-07-09
申请号：US13013220
申请日：2011-01-25
申请人： Chuanzhao Yu , Luis J. Briones
发明人： Chuanzhao Yu , Luis J. Briones
IPC分类号： G05F1/44 , G05F3/26
CPC分类号： G05F1/575
摘要： Apparatus for voltage regulation circuits and related operating methods are provided. An exemplary voltage regulation circuit includes a voltage regulation arrangement that provides a regulated output voltage based on an input voltage reference, a phase compensation arrangement coupled to the voltage regulation arrangement and configured to increase a phase margin of the voltage regulation arrangement, and detection circuitry coupled to the phase compensation arrangement. The detection circuitry is configured to disable the phase compensation arrangement in response to detecting an output current that is less than a threshold value.
摘要翻译：提供了用于调压电路和相关操作方法的装置。示例性电压调节电路包括电压调节装置，其基于输入电压基准提供调节的输出电压;耦合到电压调节装置的相位补偿装置，并且被配置为增加电压调节装置的相位裕度，以及耦合的检测电路到相位补偿装置。检测电路被配置为响应于检测到小于阈值的输出电流而禁用相位补偿装置。

5. 发明授权

US07415260B2 Current-mode direct conversion receiver 有权
标题翻译：电流模式直接转换接收器
公开(公告)号：US07415260B2
公开(公告)日：2008-08-19
申请号：US10795740
申请日：2004-03-08
申请人： Troy L. Stockstad , Klaas Wortel , Luis J. Briones , David Lovelace
发明人： Troy L. Stockstad , Klaas Wortel , Luis J. Briones , David Lovelace
IPC分类号： H04B1/00
CPC分类号： H04B1/30
摘要： A current-mode direct conversion RF receiver is presented. In one set of embodiments the RF receiver comprises a simple transconductor input stage to create a current-mode modulated signal from a voltage-mode modulated signal. A downconversion mixer may be coupled to the transconductor input stage via a low impedance current cascode stage, and may operate to create a set of current-mode quadrature baseband signals from the current-mode modulated signal. The downconversion mixer may be implemented with a transistor-switching network, which may be driven by a phase locked loop (PLL) with quadrature outputs. The set of current-mode quadrature baseband signals may be converted back to the voltage domain by a transimpedance filter, which may perform channel selection for the receiver. The transimpedance filter may additionally include a low frequency zero to remove DC offsets. The receiver may be implemented using CMOS design technologies and operated with minimal self-mixing effects, minimal DC offset in the baseband signal, and utilizing low voltages.
摘要翻译：提出了一种电流模式直接转换RF接收机。在一组实施例中，RF接收机包括简单的跨导体输入级，以从电压模式调制信号产生电流模式调制信号。下变频混频器可以经由低阻抗电流共源共栅级耦合到跨导体输入级，并且可以操作以从当前模式调制信号创建一组电流模式正交基带信号。下变频混频器可以用晶体管切换网络来实现，其可以由具有正交输出的锁相环（PLL）来驱动。电流模式正交基带信号的集合可以通过跨阻滤波器转换回电压域，该跨阻滤波器可以对接收机执行信道选择。跨阻滤波器可以另外包括用于去除DC偏移的低频零点。接收机可以使用CMOS设计技术来实现，并且以最小的自混合效应，基带信号中的最小DC偏移和利用低电压进行操作。

6. 发明授权

US07043222B2 FSK modulator using IQ up-mixers and sinewave coded DACs 有权
标题翻译： FSK调制器使用IQ上变频器和正弦波编码DAC
公开(公告)号：US07043222B2
公开(公告)日：2006-05-09
申请号：US10653322
申请日：2003-09-02
申请人： Klaas Wortel , Luis J. Briones , Troy L. Stockstad
发明人： Klaas Wortel , Luis J. Briones , Troy L. Stockstad
IPC分类号： H04B1/10
CPC分类号： H04L27/12
摘要： A radio transmitter system designed using an FSK modulator with IQ up-mixers and sinewave coded digital-to-analog converters (DACs). The radio transmitter system may include a frequency shift keying (FSK) coding logic circuit coupled to the inputs of an IQ modulation and image reject up-mixer through a respective DAC and a respective low pass filter (LPF) for each the I and the Q channels. The FSK modulation scheme may employ sine and cosine signals for the I and Q channels, respectively, where the sine and cosine waves are directly coded into the DACs. The coded levels required by the DACs may be generated using current sources and may be Gray-coded. The output of the IQ modulation and image reject up-mixer may be connected to a power amplifier, which may be used to transmit the modulated RF signal via a loop antenna.
摘要翻译：无线电发射机系统使用具有IQ上变频器和正弦波编码的数模转换器（DAC）的FSK调制器设计。无线电发射机系统可以包括频移键控（FSK）编码逻辑电路，其通过相应的DAC和针对I和Q的每个的相应的低通滤波器（LPF）耦合到IQ调制和图像拒绝上混频器的输入频道 FSK调制方案可以分别将正弦和余弦信号用于I和Q通道，其中正弦和余弦波被直接编码到DAC中。 DAC所需的编码电平可以使用电流源生成，并且可以是灰色编码的。 IQ调制和图像拒绝上混频器的输出可以连接到功率放大器，功率放大器可以用于经由环形天线发送经调制的RF信号。

7. 发明申请

US20090116472A1 Initiation of High Speed Overlay Mode for Burst Data and Real Time Streaming (Audio) Applications 有权
标题翻译：启动突发数据和实时流（音频）应用的高速覆盖模式
公开(公告)号：US20090116472A1
公开(公告)日：2009-05-07
申请号：US11935023
申请日：2007-11-05
申请人： Kuor-Hsin Chang , Clinton C. Powell , Luis J. Briones
发明人： Kuor-Hsin Chang , Clinton C. Powell , Luis J. Briones
IPC分类号： H04B7/005 , H04B1/69 , H04J3/06
CPC分类号： H04L1/0023 , H04L25/0262
摘要： In a wireless 802.15.4 communication system, a method and system are provided for switching between a predetermined protocol transmission mode and a high-speed transmission mode by including signaling mode information in a data packet (330, 340) to instruct the receiver device (300) to demodulate at least a data payload using the predetermined transmission mode if the signaling mode information comprises a first predetermined value, and to demodulate at least the data payload using the high-speed transmission mode if the signaling mode information comprises a second predetermined value. The signaling mode information may be included in the SFD field of an 802.15.4 SHR structure to instruct the receiver how to demodulate or process the data packet, or may be included as desired anywhere in the data packet to instruct the receiver how to demodulate or process one or more subsequent data packets.
摘要翻译：在无线802.15.4通信系统中，提供了一种方法和系统，用于通过在数据分组（330,340）中包括信令模式信息来在预定协议传输模式和高速传输模式之间切换以指示接收机设备 300）如果所述信令模式信息包括第一预定值，则使用所述预定传输模式来解调至少一个数据有效载荷，并且如果所述信令模式信息包括第二预定值，则使用所述高速传输模式至少解调所述数据有效载荷。信令模式信息可以包括在802.15.4 SHR结构的SFD字段中，以指示接收机如何解调或处理数据分组，或者可以根据需要在数据分组中随时包括以指示接收机如何解调或处理一个或多个后续数据包。

8. 发明授权

US06806742B1 Phase detector for low power applications 有权
标题翻译：低功率应用的相位检测器
公开(公告)号：US06806742B1
公开(公告)日：2004-10-19
申请号：US10444670
申请日：2003-05-23
申请人： Luis J. Briones , Klaas Wortel
发明人： Luis J. Briones , Klaas Wortel
IPC分类号： G01R2500
CPC分类号： H03L7/091 , G01R25/00 , H03D13/006
摘要： A low-power phase detector with differential output may comprise a control signal generator. In one embodiment, two cyclic waveforms whose phase relationship is to be measured may be input to a control signal generator. The control signal generator may output a first control signal corresponding to the first cyclic waveform such that the control signal is de-asserted at a specific point with respect to the first cyclic waveform. For example, the control signal may be de-asserted corresponding to the rising edge of the first cyclic waveform. The control signal generator may also output a second control signal corresponding to the second cyclic waveform such that the control signal is asserted at a specific point with respect to the second cyclic waveform. For example, the control signal may be asserted corresponding to the falling edge of the second cyclic waveform.
摘要翻译：具有差分输出的低功率相位检测器可以包括控制信号发生器。在一个实施例中，可将相位关系要测量的两个循环波形输入到控制信号发生器。控制信号发生器可以输出对应于第一循环波形的第一控制信号，使得控制信号在相对于第一循环波形的特定点处被解除断言。例如，控制信号可以对应于第一循环波形的上升沿被解除断言。控制信号发生器还可输出对应于第二循环波形的第二控制信号，使得控制信号在相对于第二循环波形的特定点被断言。例如，可以根据第二循环波形的下降沿来确定控制信号。

9. 发明授权

US07990937B2 Initiation of high speed overlay mode for burst data and real time streaming (audio) applications 有权
标题翻译：启动突发数据和实时流（音频）应用的高速覆盖模式
公开(公告)号：US07990937B2
公开(公告)日：2011-08-02
申请号：US11935023
申请日：2007-11-05
申请人： Kuor-Hsin Chang , Clinton C Powell , Luis J. Briones
发明人： Kuor-Hsin Chang , Clinton C Powell , Luis J. Briones
IPC分类号： H04W4/00 , H04J3/06 , H04B1/38 , H04L7/04
CPC分类号： H04L1/0023 , H04L25/0262
摘要： In a wireless 802.15.4 communication system, a method and system are provided for switching between a predetermined protocol transmission mode and a high-speed transmission mode by including signaling mode information in a data packet (330, 340) to instruct the receiver device (300) to demodulate at least a data payload using the predetermined transmission mode if the signaling mode information comprises a first predetermined value, and to demodulate at least the data payload using the high-speed transmission mode if the signaling mode information comprises a second predetermined value. The signaling mode information may be included in the SFD field of an 802.15.4 SHR structure to instruct the receiver how to demodulate or process the data packet, or may be included as desired anywhere in the data packet to instruct the receiver how to demodulate or process one or more subsequent data packets.
摘要翻译：在无线802.15.4通信系统中，提供了一种方法和系统，用于通过在数据分组（330,340）中包括信令模式信息来在预定协议传输模式和高速传输模式之间切换以指示接收机设备 300）如果所述信令模式信息包括第一预定值，则使用所述预定传输模式来解调至少一个数据有效载荷，并且如果所述信令模式信息包括第二预定值，则使用所述高速传输模式至少解调所述数据有效载荷。信令模式信息可以包括在802.15.4 SHR结构的SFD字段中，以指示接收机如何解调或处理数据分组，或者可以根据需要在数据分组中随时包括以指示接收机如何解调或处理一个或多个后续数据包。

10. 发明授权

US07433442B2 Linear half-rate clock and data recovery (CDR) circuit 有权
标题翻译：线性半速率时钟和数据恢复（CDR）电路
公开(公告)号：US07433442B2
公开(公告)日：2008-10-07
申请号：US10947891
申请日：2004-09-23
申请人： Luis J. Briones
发明人： Luis J. Briones
IPC分类号： H03D3/24
CPC分类号： H03D13/003 , H04L7/033
摘要： A linear, half-rate clock and data recovery (CDR) circuit for recovering clock information embedded in a received data signal. The half-rate CDR circuit comprises a phase detector that may receive the data signal and generate a phase error signal representative of the phase difference between the received data signal and a clock signal produced by a voltage-controlled oscillator (VCO) of the CDR circuit. The half-rate CDR typically changes the frequency of the clock signal and generates a clock signal that is aligned with the baud center of the received data signal. More specifically, when the half-rate CDR circuit is in a locked condition, both the rising and falling edges of the clock signal are aligned with the baud center of the received data signal. The half-rate CDR preferably generates a clock signal with an average frequency that is half the data rate of a received data signal.
摘要翻译：用于恢复嵌入在接收数据信号中的时钟信息的线性半速率时钟和数据恢复（CDR）电路。半速率CDR电路包括相位检测器，其可以接收数据信号并产生表示接收数据信号与由CDR电路的压控振荡器（VCO）产生的时钟信号之间的相位差的相位误差信号。半速率CDR通常改变时钟信号的频率并产生与所接收的数据信号的波特中心对准的时钟信号。更具体地，当半速率CDR电路处于锁定状态时，时钟信号的上升沿和下降沿均与接收数据信号的波特中心对准。半速率CDR优选地生成具有接收数据信号的数据速率的一半的平均频率的时钟信号。

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