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1. 发明授权

US06438613B1 Method and apparatus for allowing packet data to be separated over multiple bus targets 失效
标题翻译：允许分组数据在多个总线目标上分离的方法和装置
公开(公告)号：US06438613B1
公开(公告)日：2002-08-20
申请号：US09012025
申请日：1998-01-22
申请人： Louise Y. Yeung , Rasoul M. Oskouy
发明人： Louise Y. Yeung , Rasoul M. Oskouy
IPC分类号： G06F1300
CPC分类号： H04Q11/0478 , G06F13/128 , H04L29/06 , H04L49/90 , H04L69/32 , H04L2012/5613 , H04L2012/5616 , H04L2012/5652
摘要： A network adapter for allowing packet data to be separated over multiple bus targets, without impact to input/output bus bandwidth or network performance, having: a bus interface circuit; a bus protocol circuit coupled to the bus interface circuit; a burst dispatcher circuit coupled to the bus protocol circuit; a network interface coupled to a read processing circuit and a write processing circuit, wherein the read processing circuit and the write processing circuit are coupled to the burst dispatcher; and, a synchronization and buffering circuit coupled to the bus protocol circuit, the burst dispatcher circuit, the read processing circuit and the write processing circuit. A method for transferring packet data between a first bus target, a second bus target, and the network adapter comprising the steps of creating a set of descriptor entries in the network adapter, wherein one descriptor entry is generated for each portion of each packet to be transmitted between either the first bus target or the second bus target, and the network adapter; and, transferring a portion of packet data from either the first bus target or the second bus target to the network adapter, wherein the bus target on which the portion of packet data is contained is described by one of the set of descriptor entries.
摘要翻译：一种用于允许分组数据在多个总线目标上分离而不影响输入/输出总线带宽或网络性能的网络适配器，具有：总线接口电路; 总线协议电路，耦合到总线接口电路; 连接到总线协议电路的突发调度器电路; 耦合到读处理电路和写处理电路的网络接口，其中所述读处理电路和所述写处理电路耦合到所述脉冲串调度器; 以及耦合到总线协议电路，脉冲串调度器电路，读取处理电路和写入处理电路的同步和缓冲电路。一种用于在第一总线目标，第二总线目标和网络适配器之间传送分组数据的方法包括以下步骤：在网络适配器中创建一组描述符条目，其中为在第一总线目标或第二总线目标之间传送的每个分组的每个部分和网络适配器生成一个描述符条目; 以及将分组数据的一部分从第一总线目标或第二总线目标传送到网络适配器，其中包含分组数据部分的总线目标由所述一组描述符条目中的一个描述。

2. 发明授权

US5931926A Method and apparatus for dynamically calculating degrees of fullness of a synchronous FIFO 失效
标题翻译：动态计算同步FIFO饱和度的方法和装置
公开(公告)号：US5931926A
公开(公告)日：1999-08-03
申请号：US966548
申请日：1997-11-10
申请人： Louise Y. Yeung , Ling Cen
发明人： Louise Y. Yeung , Ling Cen
IPC分类号： G06F13/12 , G06F5/10 , G06F5/12 , G06F13/00
CPC分类号： G06F5/10
摘要： An interface circuit, coupled between a first circuitry that is synchronous to a first clock (sclk) and a second circuitry that is synchronous to a second clock (mclk), for transferring data between the first and second circuitry and achieving a fast turn-around time between a data request from the mclk domain circuitry and a bus request in the sclk domain. A first FIFO buffer for transferring data from the first circuitry to the second circuitry is provided. Logic associated with the first FIFO to synchronize reads and writes to the first FIFO is also provided. A read Bus Request Enable Generator provides a read bus request enable signal to the first circuitry, and an At.sub.-- least.sub.-- x.sub.-- words.sub.-- filled Flag Generator provides a plurality of flags, which indicate degrees of fullness of the first FIFO buffer to the second circuitry. A second FIFO buffer transfers data from the second circuitry to the first circuitry. Associated logic for synchronizing reads and writes to the second FIFO buffer is provided. A write Bus Request Enable Generator provides a write bus request enable signal to the first circuitry, and an At.sub.-- least.sub.-- y.sub.-- words.sub.-- empty Flag Generator provides a plurality of flags, which indicate degrees of emptiness of the second buffer to the second circuitry.
摘要翻译：耦合在与第一时钟（sclk）同步的第一电路和与第二时钟（mclk）同步的第二电路之间的接口电路，用于在第一和第二电路之间传送数据并实现快速转向来自mclk域电路的数据请求与sclk域中的总线请求之间的时间。提供了用于将数据从第一电路传送到第二电路的第一FIFO缓冲器。还提供了与第一FIFO相关联的与第一FIFO同步读取和写入的逻辑。读总线请求使能发生器向第一电路提供读总线请求使能信号，并且至少x字字填充的标志生成器提供多个标志，其指示第一FIFO缓冲器的饱和度到第二电路。第二FIFO缓冲器将数据从第二电路传送到第一电路。提供了用于使读取和写入到第二FIFO缓冲器的相关逻辑。写总线请求使能发生器向第一电路提供写总线请求使能信号，并且至少y字空标志发生器提供多个标志，其指示第二缓冲器到第二电路的空闲程度。

3. 发明授权

US5793953A Method and apparatus for allowing packet data to be separated over multiple bus targets 失效
标题翻译：允许分组数据在多个总线目标上分离的方法和装置
公开(公告)号：US5793953A
公开(公告)日：1998-08-11
申请号：US499199
申请日：1995-07-07
申请人： Louise Y. Yeung , Rasoul M. Oskouy
发明人： Louise Y. Yeung , Rasoul M. Oskouy
IPC分类号： G06F13/00 , G06F13/12 , H04L12/56 , H04L29/06 , H04L29/08 , H04Q11/04
CPC分类号： H04Q11/0478 , G06F13/128 , H04L29/06 , H04L49/90 , H04L2012/5613 , H04L2012/5616 , H04L2012/5652 , H04L69/32
摘要： A network adapter for allowing packet data to be separated over multiple bus targets without impact to input/output bus bandwidth or network performance, having: a bus interface circuit; a bus protocol circuit coupled to the bus interface circuit; a burst dispatcher circuit coupled to the bus protocol circuit; a network interface coupled to a read processing circuit and a write processing circuit, wherein the read processing circuit and the write processing circuit are coupled to the burst dispatcher; and, a synchronization and buffering circuit coupled to the bus protocol circuit, the burst dispatcher circuit, the read processing circuit and the write processing circuit.
摘要翻译：一种用于允许分组数据在多个总线目标上分离而不影响输入/输出总线带宽或网络性能的网络适配器，具有：总线接口电路; 总线协议电路，耦合到总线接口电路; 连接到总线协议电路的突发调度器电路; 耦合到读处理电路和写处理电路的网络接口，其中所述读处理电路和所述写处理电路耦合到所述脉冲串调度器; 以及耦合到总线协议电路，脉冲串调度器电路，读取处理电路和写入处理电路的同步和缓冲电路。

4. 发明授权

US5046182A Code points for transferring data from a network transmission medium to a station on the network 失效
标题翻译：用于将数据从网络传输介质传输到网络上的站的代码点
公开(公告)号：US5046182A
公开(公告)日：1991-09-03
申请号：US444561
申请日：1989-12-01
申请人： James R. Hamstra , Ronald S. Perloff , Louise Y. Yeung
发明人： James R. Hamstra , Ronald S. Perloff , Louise Y. Yeung
IPC分类号： H04B10/20 , H04L1/00 , H04L7/04 , H04L12/433 , H04L29/02
CPC分类号： H04L12/433
摘要： Apparatus and methods for encoding information characters received by a station from a transmission medium to generate internal code points for retrieval or retransmission by the station. The encoding provides an internal symbol set that is able to pass complete line state information via its internal code points, thereby eliminating the need for extra signals to indicate the current line state. The code points can also report error situations, such as elasticity buffer errors, and can be accepted by the station's transmitter to be encoded and, after appropriate filtering, repeated onto the transmission medium. The internal code points are optimized so that the code point set minimizes the decoding logic at the receiving end, be it the station's Media Access Control function or its transmitter. Furthermore, internally, the station may make use of the internal code points to synchronize the receiver elasticity buffer.

5. 发明授权

US06226698B1 Method and apparatus for dynamically calculating degrees of fullness of a synchronous FIFO 有权
标题翻译：动态计算同步FIFO饱和度的方法和装置
公开(公告)号：US06226698B1
公开(公告)日：2001-05-01
申请号：US09151364
申请日：1998-09-11
申请人： Louise Y. Yeung , Ling Cen
发明人： Louise Y. Yeung , Ling Cen
IPC分类号： B06F1300
CPC分类号： G06F5/10
摘要： An interface circuit, coupled between a first circuitry that is synchronous to a first clock (sclk) and a second circuitry that is synchronous to a second clock (mclk), for transferring data between the first and second circuitry and achieving a fast turn-around time between a data request from the mclk domain circuitry and a bus request in the sclk domain. A first FIFO buffer for transferring data from the first circuitry to the second circuitry is provided. Logic associated with the first FIFO to synchronize reads and writes to the first FIFO is also provided. A read Bus Request Enable Generator provides a read bus request enable signal to the first circuitry, and an At_least_x_words_filled Flag Generator provides a plurality of flags, which indicate degrees of fullness of the first FIFO buffer to the second circuitry. A second FIFO buffer transfers data from the second circuitry to the first circuitry. Associated logic for synchronizing reads and writes to the second FIFO buffer is provided. A write Bus Request Enable Generator provides a write bus request enable signal to the first circuitry, and an At_least_y_words_empty Flag Generator provides a plurality of flags, which indicate degrees of emptiness of the second buffer to the second circuitry.
摘要翻译：耦合在与第一时钟（sclk）同步的第一电路和与第二时钟（mclk）同步的第二电路之间的接口电路，用于在第一和第二电路之间传送数据并实现快速转向来自mclk域电路的数据请求与sclk域中的总线请求之间的时间。提供了用于将数据从第一电路传送到第二电路的第一FIFO缓冲器。还提供了与第一FIFO相关联的与第一FIFO同步读取和写入的逻辑。读总线请求使能生成器向第一电路提供读总线请求使能信号，并且At_least_x_words_filled标志生成器提供多个标志，其指示第一FIFO缓冲器到第二电路的充满度。第二FIFO缓冲器将数据从第二电路传送到第一电路。提供了用于使读取和写入到第二FIFO缓冲器的相关逻辑。写总线请求使能生成器向第一电路提供写总线请求使能信号，并且At_least_y_words_empty标志生成器提供多个标志，其指示第二缓冲器对第二电路的空虚度。

6. 发明授权

US5185863A Byte-wide elasticity buffer 失效
标题翻译： BYTE-WIDE ELASTICITY BUFFER
公开(公告)号：US5185863A
公开(公告)日：1993-02-09
申请号：US444619
申请日：1989-12-01
申请人： James R. Hamstra , Ronald S. Perloff , Louise Y. Yeung
发明人： James R. Hamstra , Ronald S. Perloff , Louise Y. Yeung
IPC分类号： G06F5/06 , H04J3/06 , H04L7/00 , H04L7/04 , H04L12/42 , H04L13/08
CPC分类号： H04J3/0632 , H04L12/422
摘要： A network station's elasticity buffer includes a memory core together with write and read pointer logic. The memory core includes a START area and a CONTINUATION area which is a cyclic buffer. Under normal conditions, the read pointer follows the write pointer cyclically in the CONTINUATION area. However, upon detection of a start delimiter or upon station reset, the pointers recenter to the START area. Separate synchronizing logic is provided for each of the two recentering modes to reduce metastability problems caused by asynchronous sampling of data. A delay-by-one mechanism is built into the start delimiter mode synchronization scheme so that, under certain conditions, the read pointer is held in the CONTINUATION area for an additional read so an early sample of the read-start signal by the station's local clock while the read pointer is well behind the write pointer will not drop the last character of the previous frame when that frame is not separated from the next start delimiter by a sufficient interframe gap. A look-ahead-look-current detector insures that the there is not too much initial separation between the write pointer and the read pointer. A delay-GO mechanism is built into the reset mode synchronization scheme to prevent irregular dropping of line state characters when the local byte clock is trapped within the metastability window while clock drift is infinitesimal. The read pointer logic also includes a mechanism for preventing the delay-GO mechanism from creating too much initial separation between the write pointer and the read pointer.

7. 发明授权

US08176304B2 Mechanism for performing function level reset in an I/O device 有权
标题翻译：在I / O设备中执行功能级别复位的机制
公开(公告)号：US08176304B2
公开(公告)日：2012-05-08
申请号：US12256250
申请日：2008-10-22
申请人： Rahoul Puri , Arvind Srinivasan , Louise Y. Yeung , Marcelino M. Dignum , John E. Watkins
发明人： Rahoul Puri , Arvind Srinivasan , Louise Y. Yeung , Marcelino M. Dignum , John E. Watkins
IPC分类号： G06F9/00 , G06F15/177 , G06F1/24 , G06F3/00 , G06F13/00
CPC分类号： G06F13/385
摘要： An I/O device having function level reset functionality includes a host interface that may include a master reset unit, a plurality of client interfaces, each corresponding to one or more functions, and a plurality of hardware resources. Each hardware resource may be associated with a respective function. In response to receiving a reset request to reset a specific function, the master reset unit may provide to each client interface, a request signal corresponding to the reset request, and a signal identifying the specific function. Each client interface having an association with the specific function may initiate a reset operation of the associated hardware resources, and also provide a client reset done signal for the specific function to the master reset unit in response to completion of the reset operations of the hardware resources. The master reset unit provides a reset done signal for the specific function to the host interface.
摘要翻译：具有功能级复位功能的I / O设备包括主机接口，其可以包括主复位单元，多个客户端接口，每个对应于一个或多个功能，以及多个硬件资源。每个硬件资源可以与相应的功能相关联。响应于接收到重置特定功能的复位请求，主复位单元可以向每个客户端接口提供对应于重置请求的请求信号，以及标识特定功能的信号。具有与特定功能的关联的每个客户端接口可以启动相关联的硬件资源的复位操作，并且响应于硬件资源的复位操作的完成，向主复位单元提供用于特定功能的客户端重置完成信号。主复位单元为主机接口提供特定功能的复位完成信号。

8. 发明申请

US20100100717A1 MECHANISM FOR PERFORMING FUNCTION LEVEL RESET IN AN I/O DEVICE 有权
标题翻译：用于在I / O设备中执行功能电平复位的机制
公开(公告)号：US20100100717A1
公开(公告)日：2010-04-22
申请号：US12256250
申请日：2008-10-22
申请人： Rahoul Puri , Arvind Srinivasan , Louise Y. Yeung , Marcelino M. Dignum , John E. Watkins
发明人： Rahoul Puri , Arvind Srinivasan , Louise Y. Yeung , Marcelino M. Dignum , John E. Watkins
IPC分类号： G06F9/00
CPC分类号： G06F13/385
摘要： An I/O device having function level reset functionality includes a host interface that may include a master reset unit, a plurality of client interfaces, each corresponding to one or more functions, and a plurality of hardware resources. Each hardware resource may be associated with a respective function. In response to receiving a reset request to reset a specific function, the master reset unit may provide to each client interface, a request signal corresponding to the reset request, and a signal identifying the specific function. Each client interface having an association with the specific function may initiate a reset operation of the associated hardware resources, and also provide a client reset done signal for the specific function to the master reset unit in response to completion of the reset operations of the hardware resources. The master reset unit provides a reset done signal for the specific function to the host interface.
摘要翻译：具有功能级复位功能的I / O设备包括主机接口，其可以包括主复位单元，多个客户端接口，每个对应于一个或多个功能，以及多个硬件资源。每个硬件资源可以与相应的功能相关联。响应于接收到重置特定功能的复位请求，主复位单元可以向每个客户端接口提供对应于重置请求的请求信号，以及标识特定功能的信号。具有与特定功能的关联的每个客户端接口可以启动相关联的硬件资源的复位操作，并且响应于硬件资源的复位操作的完成，向主复位单元提供用于特定功能的客户端重置完成信号。主复位单元为主机接口提供特定功能的复位完成信号。

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