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1. 发明授权

US08085079B2 Summing circuit for a filter 有权
标题翻译：滤波器的求和电路
公开(公告)号：US08085079B2
公开(公告)日：2011-12-27
申请号：US12832844
申请日：2010-07-08
申请人： Kelvin Tran , Matthias Bussmann , Lloyd Linder , Salam Elahmadi , Harry Tan
发明人： Kelvin Tran , Matthias Bussmann , Lloyd Linder , Salam Elahmadi , Harry Tan
IPC分类号： H03K17/60 , H03M1/66
CPC分类号： H03H15/00
摘要： According to one embodiment of the invention, a summing circuit comprises a first transmitter, a second transmitter, a first current offset circuit and a first transconductance amplifier. The first current offset circuit is coupled to the emitters of the first and second transistors. The first transconductance amplifier is coupled to the first current offset circuit.
摘要翻译：根据本发明的一个实施例，求和电路包括第一发射机，第二发射机，第一电流偏移电路和第一跨导放大器。第一电流偏移电路耦合到第一和第二晶体管的发射极。第一跨导放大器耦合到第一电流偏移电路。

2. 发明申请

US20090279893A1 ANALOG FINITE IMPULSE RESPONSE FILTER 有权
标题翻译：模拟有限脉冲响应滤波器
公开(公告)号：US20090279893A1
公开(公告)日：2009-11-12
申请号：US12119394
申请日：2008-05-12
申请人： Kelvin Tran , Matthias Bussmann , Lloyd Linder , Salam Elahmadi , Harry Tan
发明人： Kelvin Tran , Matthias Bussmann , Lloyd Linder , Salam Elahmadi , Harry Tan
IPC分类号： H04J14/02
CPC分类号： H03H15/00
摘要： According to one embodiment of the invention, a programmable finite impulse response (FIR) filter is implemented with differential isolation circuits to isolate parasitic capacitance from attenuating an output signal at both a first and second differential output terminals of the FIR filter. The FIR includes a track and hold circuit and a summing circuit that provides operational advantages to the FIR filter.
摘要翻译：根据本发明的一个实施例，利用差分隔离电路实现可编程有限脉冲响应（FIR）滤波器，以隔离寄生电容，从而在FIR滤波器的第一和第二差分输出端两端衰减输出信号。 FIR包括跟踪和保持电路以及为FIR滤波器提供操作优势的求和电路。

3. 发明申请

US20050038846A1 Substraction circuit with a dummy digital to analog converter 审中-公开
标题翻译：具有虚拟数模转换器的抽象电路
公开(公告)号：US20050038846A1
公开(公告)日：2005-02-17
申请号：US10847433
申请日：2004-05-17
申请人： Don Devendorf , Benjamin Felder , Erick Hirata , Christopher Langit , Lloyd Linder
发明人： Don Devendorf , Benjamin Felder , Erick Hirata , Christopher Langit , Lloyd Linder
IPC分类号： G06G7/00 , G06G7/14 , H03M1/06 , H03M1/16
CPC分类号： G06G7/14 , H03M1/0678 , H03M1/167
摘要： A subtraction circuit. The novel subtraction circuit includes a first circuit for providing an impedance between an input node and an output node, a second circuit for generating a first current and applying the first current to the output node to produce a desired voltage drop between the input and output nodes, and a third circuit for independently generating a second current relative to the first current and applying the second current to the input node to regulate a current input to the first circuit at the input node. The second and third circuits are implemented using two digital to analog converters (DACs), a precision DAC for generating the first current and a non-trimmed “dummy” DAC for generating the second current. In an illustrative embodiment, the subtraction circuit is used in the reconstruction stage of a subranging analog to digital converter.
摘要翻译：减法电路。该新颖的减法电路包括用于在输入节点和输出节点之间提供阻抗的第一电路，用于产生第一电流并将第一电流施加到输出节点以在输入和输出节点之间产生期望电压降的第二电路以及第三电路，用于独立地产生相对于第一电流的第二电流，并且将第二电流施加到输入节点以调节在输入节点处的到第一电路的电流输入。第二和第三电路使用两个数模转换器（DAC），用于产生第一电流的精密DAC和用于产生第二电流的非修整的“虚拟”DAC来实现。在说明性实施例中，减法电路用于子阵列模数转换器的重建阶段。

4. 发明申请

US20050035791A1 Sample and hold circuit and bootstrapping circuits therefor 有权
标题翻译：采样保持电路和自举电路
公开(公告)号：US20050035791A1
公开(公告)日：2005-02-17
申请号：US10863561
申请日：2004-06-08
申请人： Don Devendorf , Lloyd Linder , Kelvin Tran
发明人： Don Devendorf , Lloyd Linder , Kelvin Tran
IPC分类号： G11C27/02 , H03K5/00
CPC分类号： G11C27/02
摘要： A sample and hold circuit including a first arrangement for receiving an input signal; a second arrangement for sampling and holding the signal in response to a control signal; and a third arrangement for minimizing the change in an input transistor's base current when the circuit switches from track to hold or hold to track and for keeping the collector emitter voltage constant at the input transistor. An arrangement is disclosed to increase the dynamic current accuracy of a current mirror for a diode connected transistor, by holding the voltage across one transistor in the current mirror constant. Another arrangement is disclosed for holding collector to emitter voltage constant for intermediate transistors resulting in improved gain accuracy and linearity. In one embodiment, a dummy leg is added to isolate the output voltage from switching transients that occur when an intermediate transistor is turned on at the transition from track to hold.
摘要翻译：一种采样和保持电路，包括用于接收输入信号的第一装置; 第二装置，用于响应于控制信号采样和保持信号; 以及当电路从轨道切换到保持或保持跟踪并且用于保持集电极发射极电压恒定在输入晶体管时，最小化输入晶体管的基极电流的变化的第三布置。公开了一种通过将电流镜中的一个晶体管的电压保持恒定来提高二极管连接晶体管的电流镜的动态电流精度的装置。公开了另一种用于将集电极保持到中间晶体管的发射极电压恒定的结构，从而提高增益精度和线性度。在一个实施例中，添加虚拟支路以将输出电压与在从轨道到保持的转变时中间晶体管导通时发生的开关瞬变隔离。

5. 发明申请

US20060082484A1 Multi-mode analog to digital converter 失效
公开(公告)号：US20060082484A1
公开(公告)日：2006-04-20
申请号：US10969283
申请日：2004-10-20
申请人： Lloyd Linder , Michael Clingempeel , William Cheng , William Rinard , Benjamin Felder
发明人： Lloyd Linder , Michael Clingempeel , William Cheng , William Rinard , Benjamin Felder
IPC分类号： H03M1/12
CPC分类号： H03M1/007 , H03M1/167
摘要： A multi-mode analog to, digital converter (ADC). The novel ADC includes an input terminal for receiving an analog input signal; a plurality of processing stages, each processing stage adapted to generate an output signal from an input to that processing stage; and a mechanism for determining a mode of operation and in accordance therewith connect the processing stages and the input terminal in a predetermined configuration. In an illustrative embodiment, the ADC can be configured as a subranging ADC, and the mechanism for determining, the mode of operation includes a signal processor for automatically selecting the mode of operation based on the frequency components of the input signal.

6. 发明授权

US07990185B2 Analog finite impulse response filter 有权
标题翻译：模拟有限脉冲响应滤波器
公开(公告)号：US07990185B2
公开(公告)日：2011-08-02
申请号：US12119394
申请日：2008-05-12
申请人： Kelvin Tran , Matthias Bussmann , Lloyd Linder , Salam Elahmadi , Harry Tan
发明人： Kelvin Tran , Matthias Bussmann , Lloyd Linder , Salam Elahmadi , Harry Tan
IPC分类号： H03M1/06 , H04B1/10 , H03K5/153
CPC分类号： H03H15/00
摘要： According to one embodiment of the invention, a programmable finite impulse response (FIR) filter is implemented with differential isolation circuits to isolate parasitic capacitance from attenuating an output signal at both first and second differential output terminals of the FIR filter. The FIR includes a track and hold circuit and a summing circuit that provides operational advantages to the FIR filter.
摘要翻译：根据本发明的一个实施例，使用差分隔离电路实现可编程有限脉冲响应（FIR）滤波器，以隔离寄生电容，从而衰减FIR滤波器的第一和第二差分输出端的输出信号。 FIR包括跟踪和保持电路以及为FIR滤波器提供操作优势的求和电路。

7. 发明申请

US20050127955A1 Low power output driver 有权
标题翻译：低功率输出驱动器
公开(公告)号：US20050127955A1
公开(公告)日：2005-06-16
申请号：US10886850
申请日：2004-07-08
申请人： Nanci Martinez , Seth Everton , Erick Hirata , Lloyd Linder
发明人： Nanci Martinez , Seth Everton , Erick Hirata , Lloyd Linder
IPC分类号： H03K17/66 , H03K19/018 , H03B1/00
CPC分类号： H03K19/01812 , H03K17/662
摘要： An output driver. The novel output driver includes a first circuit for receiving an input signal and in accordance therewith generating an output signal at an output node, a second circuit for applying a variable current to the output node, and a third circuit for controlling the magnitude of the variable current in accordance with the input signal. In an illustrative embodiment, the third circuit is adapted to generate a controlling current in accordance with the input signal, and the second circuit includes a current mirror adapted to receive the controlling current and output a scaled version of the controlling current to the output node.
摘要翻译：输出驱动程序新颖的输出驱动器包括用于接收输入信号并根据其在输出节点处产生输出信号的第一电路，用于向输出节点施加可变电流的第二电路和用于控制变量的幅度的第三电路电流根据输入信号。在说明性实施例中，第三电路适于根据输入信号产生控制电流，并且第二电路包括适于接收控制电流的电流镜，并将控制电流的缩放版本输出到输出节点。

8. 发明申请

US20050035821A1 High speed, high resolution amplifier topology 有权
标题翻译：高速，高分辨率放大器拓扑
公开(公告)号：US20050035821A1
公开(公告)日：2005-02-17
申请号：US10740172
申请日：2003-12-18
申请人： Seth Everton , Lloyd Linder , Michael Liou , Tom Spargo , Kelvin Tran
发明人： Seth Everton , Lloyd Linder , Michael Liou , Tom Spargo , Kelvin Tran
IPC分类号： H03F1/02 , H03F1/32 , H03F3/45
CPC分类号： H03F3/45179 , H03F1/0233 , H03F1/3211 , H03F3/45089 , H03F2203/45674
摘要： An amplifier. The novel amplifier includes a first circuit for receiving and amplifying an input signal and outputting an output signal, and a second circuit for supplying power to the first circuit, wherein the power supplied varies in accordance with variations in the output signal. The second circuit includes a bootstrapping circuit adapted to regulate the voltages across any transistors in the signal path such that the voltages remain constant. In an illustrative embodiment, the second circuit bootstraps the voltages across a PMOS current source that acts as the load to an input stage, as well as a Darlington pair in an output stage of the amplifier.
摘要翻译：放大器新型放大器包括用于接收和放大输入信号并输出输出信号的第一电路和用于向第一电路供电的第二电路，其中所提供的功率根据输出信号的变化而变化。第二电路包括自举电路，其适于调节信号路径中的任何晶体管上的电压，使得电压保持恒定。在说明性实施例中，第二电路将用作负载的PMOS电流源两端的电压引导到放大器的输出级中的达林顿对。

9. 发明申请

US20050035790A1 High speed switch 有权
标题翻译：高速开关
公开(公告)号：US20050035790A1
公开(公告)日：2005-02-17
申请号：US10740173
申请日：2003-12-18
申请人： Don Devendorf , Seth Everton , Lloyd Linder , Michael Liou
发明人： Don Devendorf , Seth Everton , Lloyd Linder , Michael Liou
IPC分类号： G11C27/02 , H03K5/153 , H03K17/041
CPC分类号： G11C27/02 , H03K17/04113
摘要： A high speed switch. The novel switch includes an input circuit having a transistor Q1 for receiving an input signal, a first mechanism for providing a path from an output of Q1 to an output terminal, and a second mechanism for receiving a control signal and in accordance therewith reducing the conductivity of the path during a mute mode. The first mechanism includes a first circuit for providing a first path from an output of Q1 to a first node, and a second circuit for providing a second path connecting the first node to the output terminal. The second mechanism is adapted to apply a signal to the first node during the mute mode such that the first and second circuits are off or partially conducting. The switch also includes a circuit for clamping the first node to a first predetermined voltage during the mute mode.
摘要翻译：高速开关新型开关包括具有用于接收输入信号的晶体管Q1的输入电路，用于提供从Q1的输出到输出端的路径的第一机构，以及用于接收控制信号的第二机构，并且根据其降低电导率在静音模式下的路径。第一机构包括用于提供从Q1的输出到第一节点的第一路径的第一电路和用于提供将第一节点连接到输出端子的第二路径的第二电路。第二机构适于在静音模式期间将信号施加到第一节点，使得第一和第二电路关闭或部分导通。开关还包括用于在静音模式期间将第一节点钳位到第一预定电压的电路。

10. 发明申请

US20100271107A1 ANALOG FINITE IMPULSE RESPONSE FILTER 有权
标题翻译：模拟有限脉冲响应滤波器
公开(公告)号：US20100271107A1
公开(公告)日：2010-10-28
申请号：US12832844
申请日：2010-07-08
申请人： Kelvin Tran , Matthias Bussmann , Lloyd Linder , Salam Elahmadi , Harry Tan
发明人： Kelvin Tran , Matthias Bussmann , Lloyd Linder , Salam Elahmadi , Harry Tan
IPC分类号： G06G7/14 , H03K5/00
CPC分类号： H03H15/00
摘要： According to one embodiment of the invention, a programmable finite impulse response (FIR) filter is implemented with differential isolation circuits to isolate parasitic capacitance from attenuating an output signal at both a first and second differential output terminals of the FIR filter. The FIR includes a summing circuit that provides operational advantages to the FIR filter.
摘要翻译：根据本发明的一个实施例，利用差分隔离电路实现可编程有限脉冲响应（FIR）滤波器，以隔离寄生电容，从而在FIR滤波器的第一和第二差分输出端两端衰减输出信号。 FIR包括对FIR滤波器提供操作优势的求和电路。

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