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1. 发明申请

US20050035892A1 SPLIT CELL BOWTIE DIGITAL TO ANALOG CONVERTER AND METHOD 失效
标题翻译：分离单元数字数字到模拟转换器和方法
公开(公告)号：US20050035892A1
公开(公告)日：2005-02-17
申请号：US10739860
申请日：2003-12-18
申请人： Don Devendorf , Erick Hirata , Lloyd Linder , Christopher Langit , Roger Kosaka
发明人： Don Devendorf , Erick Hirata , Lloyd Linder , Christopher Langit , Roger Kosaka
IPC分类号： H03M1/06 , H03M1/74 , H03M1/80
CPC分类号： H03M1/0643 , H03M1/745
摘要： A DAC (10) including an operational amplifier (12) having an input terminal; a plurality of current paths coupled to the input terminal; a plurality of current sources (I1/2-I4/2); and an arrangement (11) for switchably coupling current from at least two of the cells to a respective one of the paths in response to an input signal. In a specific embodiment, the inventive DAC (10) further includes a first resistive element (2R1-2R4) disposed in each of the current paths, a second resistive element (R1-R4) disposed between the current paths, and a feedback resistor (RF) disposed between an output terminal of the amplifier and the input terminal thereof. In the illustrative embodiment, the coupling arrangement includes a plurality of switches (SW1-SW4); each of the switches is adapted to switch half of the current from a first source and half of the current from a second source into a respective one of the paths. The invention is adapted to lower the distortion of digital to analog converters by improving differential nonlinearities and integral nonlinearities, caused primarily by current source gradient errors, without the need for trimming.
摘要翻译：包括具有输入端的运算放大器（12）的DAC（10）耦合到所述输入端的多个电流通路; 多个电流源（I1 / 2-I4 / 2）; 以及用于响应于输入信号将来自至少两个单元的电流可切换地耦合到相应的一个路径的装置（11）。在具体实施例中，本发明的DAC（10）还包括设置在每个电流路径中的第一电阻元件（2R1-2R4），设置在电流路径之间的第二电阻元件（R1-R4）和反馈电阻器 RF）设置在放大器的输出端和其输入端之间。在说明性实施例中，耦合装置包括多个开关（SW1-SW4）; 每个开关适于将来自第一源的电流的一半和来自第二源的电流的一半切换到相应的一个路径。本发明适用于通过改善主要由电流源梯度误差引起的差分非线性和积分非线性来降低数模转换器的失真，而不需要修整。

2. 发明申请

US20050035788A1 Clamped comparator 审中-公开
标题翻译：钳位比较器
公开(公告)号：US20050035788A1
公开(公告)日：2005-02-17
申请号：US10740334
申请日：2003-12-18
申请人： Don Devendorf , Erick Hirata , Robert Horhota , Christopher Langit , Lloyd Linder , Phung Phan
发明人： Don Devendorf , Erick Hirata , Robert Horhota , Christopher Langit , Lloyd Linder , Phung Phan
IPC分类号： H03D1/00
CPC分类号： H03M1/08 , H03F3/4508 , H03F3/45085 , H03F2203/45144 , H03F2203/45332 , H03F2203/45702 , H03M1/38
摘要： A clamped comparator. The novel comparator includes a first circuit for comparing first and second input signals and generating a digital output, and a second circuit for receiving a control signal and in accordance therewith decoupling the input signals from the output. The second circuit includes one or more switching circuits adapted to clamp the signal path between the input signals and the output when the circuit is operating in a ‘mute’ mode. In an illustrative embodiment, the comparator also includes a pre-amplifier with an amplifier stage, and the switching circuit is adapted to turn off the amplifier stage and/or steer the outputs of the amplifier stage out of the signal path, when the circuit is in the ‘mute’ mode.
摘要翻译：钳位比较器。新颖的比较器包括用于比较第一和第二输入信号并产生数字输出的第一电路，以及用于接收控制信号并根据输入信号去耦的输出的第二电路。第二电路包括一个或多个开关电路，其适于在电路以“静音”模式操作时将输入信号和输出之间的信号路径钳位。在说明性实施例中，比较器还包括具有放大器级的前置放大器，并且该开关电路适于在放大器级放大器级和/或引导放大器级的输出从信号通路传出时，当电路为在“静音”模式。

3. 发明申请

US20050038846A1 Substraction circuit with a dummy digital to analog converter 审中-公开
标题翻译：具有虚拟数模转换器的抽象电路
公开(公告)号：US20050038846A1
公开(公告)日：2005-02-17
申请号：US10847433
申请日：2004-05-17
申请人： Don Devendorf , Benjamin Felder , Erick Hirata , Christopher Langit , Lloyd Linder
发明人： Don Devendorf , Benjamin Felder , Erick Hirata , Christopher Langit , Lloyd Linder
IPC分类号： G06G7/00 , G06G7/14 , H03M1/06 , H03M1/16
CPC分类号： G06G7/14 , H03M1/0678 , H03M1/167
摘要： A subtraction circuit. The novel subtraction circuit includes a first circuit for providing an impedance between an input node and an output node, a second circuit for generating a first current and applying the first current to the output node to produce a desired voltage drop between the input and output nodes, and a third circuit for independently generating a second current relative to the first current and applying the second current to the input node to regulate a current input to the first circuit at the input node. The second and third circuits are implemented using two digital to analog converters (DACs), a precision DAC for generating the first current and a non-trimmed “dummy” DAC for generating the second current. In an illustrative embodiment, the subtraction circuit is used in the reconstruction stage of a subranging analog to digital converter.
摘要翻译：减法电路。该新颖的减法电路包括用于在输入节点和输出节点之间提供阻抗的第一电路，用于产生第一电流并将第一电流施加到输出节点以在输入和输出节点之间产生期望电压降的第二电路以及第三电路，用于独立地产生相对于第一电流的第二电流，并且将第二电流施加到输入节点以调节在输入节点处的到第一电路的电流输入。第二和第三电路使用两个数模转换器（DAC），用于产生第一电流的精密DAC和用于产生第二电流的非修整的“虚拟”DAC来实现。在说明性实施例中，减法电路用于子阵列模数转换器的重建阶段。

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