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1. 发明授权

US07565461B2 Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers 有权
标题翻译：交换机/网络适配器端口将可重配置处理元件耦合到一个或多个微处理器以与交错存储器控制器一起使用
公开(公告)号：US07565461B2
公开(公告)日：2009-07-21
申请号：US11203983
申请日：2005-08-15
申请人： Jon M. Huppenthal , Thomas R. Seeman , Lee A. Burton
发明人： Jon M. Huppenthal , Thomas R. Seeman , Lee A. Burton
IPC分类号： G06F3/00
CPC分类号： G06F13/385 , G06F13/1652
摘要： A switch/network adapter port (“SNAP™”) in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format for clustered computers employing multi-adaptive processor (“MAP®”, both trademarks of SRC Computers, Inc.) elements for use with interleaved memory controllers. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format adapter port coupled to a reconfigurable processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (“FPGA”) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.
摘要翻译：双串行内存模块（“DIMM”）或Rambus（TM）在线内存模块（“RIMM”）格式的交换机/网络适配器端口（“SNAP（TM）”），用于采用多自适应处理器（“MAP（R）”，SRC Computers，Inc.的两个商标）用于交错存储器控制器的元件。特别公开的是基于微处理器的计算机系统，其利用耦合到可重构处理器元件的DIMM或RIMM物理格式适配器端口来实现到外部交换机，网络或其他设备的连接。在特定实施例中，连接可以被提供给PCI，加速图形端口（“AGP”）或系统维护（“SM”）总线，用于将控制信息传递到主微处理器或其他控制芯片。基于现场可编程门阵列（“FPGA”）的处理元件具有将数据传送到外部互连结构或设备的能力。

2. 发明授权

US07424552B2 Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices 有权
标题翻译：包括由直接执行逻辑元件和一个或多个密集逻辑设备可选地访问的共享存储器资源的交换机/网络适配器端口
公开(公告)号：US07424552B2
公开(公告)日：2008-09-09
申请号：US10618041
申请日：2003-07-11
申请人： Lee A. Burton
发明人： Lee A. Burton
IPC分类号： G06F15/16
CPC分类号： G06F13/385 , G06F2213/3808
摘要： An enhanced switch/network adapter port (“SNAP™”) including collocated shared memory resources (“SNAPM™”) in a dual in-line memory module (“DIMM”) or any other memory module format for clustered computing systems employing direct execution logic such as multi-adaptive processor elements (“MAP®”, all trademarks of SRC Computers, Inc.). Functionally, the SNAPM modules incorporate and properly allocate memory resources so that the memory appears to the associated dense logic device(s) (e.g. a microprocessor) to be functionally like any other system memory such that no time penalties are incurred when accessing it. Through the use of a programmable access coordination mechanism, the control of this memory can be handed off to the SNAPM memory controller and, once in control, the controller can move data between the shared memory resources and the computer network such that the transfer is performed at the maximum rate that the memory devices themselves can sustain. This provides the highest performance link to the other network devices such as MAP® elements, common memory boards and the like.
摘要翻译：包括双列直插式存储器模块（“DIMM”）中的并置共享存储器资源（“SNAPM TM”）或集群计算的任何其它存储器模块格式的增强型交换机/网络适配器端口（“SNAP（TM）”）采用直接执行逻辑的系统，例如多自适应处理器元件（“MAP”，SRC Computers，Inc.的所有商标））。在功能上，SNAPM模块并入并正确地分配存储器资源，使得相关联的密集逻辑设备（例如微处理器）的存储器在功能上与任何其他系统存储器一样，使得在访问时不会引起时间惩罚。通过使用可编程访问协调机制，可以将该存储器的控制权交给SNAPM存储器控制器，一旦控制，控制器可以在共享存储器资源和计算机网络之间移动数据，从而执行传输以存储器件本身可以承受的最大速率。这提供了与其他网络设备（例如MAP（R）），公共存储器板等的最高性能链接。

3. 发明授权

US07373440B2 Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format 有权
标题翻译：用于使用双列直插式存储器模块格式的多自适应处理器链的集群计算机的交换机/网络适配器端口
公开(公告)号：US07373440B2
公开(公告)日：2008-05-13
申请号：US09932330
申请日：2001-08-17
申请人： Jon M. Huppenthal , Thomas R. Seeman , Lee A. Burton
发明人： Jon M. Huppenthal , Thomas R. Seeman , Lee A. Burton
IPC分类号： G06F13/12
CPC分类号： G06F15/7867 , G06F13/4027
摘要： A switch/network adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to significantly enhance data transfer rates over that otherwise available through use of the standard peripheral component interconnect (“PCI”) bus. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (“FPGA”) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.
摘要翻译：在双列直插式存储器模块（“DIMM”）中使用采用多自适应处理器（“MAP”）（SRC Computers，Inc.的商标）的集群计算机的交换机/网络适配器端口（“SNAP” 或Rambus（TM）在线存储器模块（“RIMM”）格式，以显着增强通过使用标准外围组件互连（“PCI”）总线可获得的数据传输速率。特别公开的是基于微处理器的计算机系统，其利用DIMM或RIMM物理格式处理器元件来实现与外部交换机，网络或其他设备的连接。在特定实施例中，连接可以被提供给PCI，加速图形端口（“AGP”）或系统维护（“SM”）总线，用于将控制信息传递到主微处理器或其他控制芯片。基于现场可编程门阵列（“FPGA”）的处理元件具有将数据传送到外部互连结构或设备的能力。

4. 发明授权

US07003593B2 Computer system architecture and memory controller for close-coupling within a hybrid processing system utilizing an adaptive processor interface port 失效
公开(公告)号：US07003593B2
公开(公告)日：2006-02-21
申请号：US10282986
申请日：2002-10-29
申请人： Jon M. Huppenthal , Thomas R. Seeman , Lee A. Burton
发明人： Jon M. Huppenthal , Thomas R. Seeman , Lee A. Burton
IPC分类号： G06F13/28
CPC分类号： G06F15/7867 , G06F13/1663
摘要： A computer system architecture and memory controller for close-coupling within a hybrid computing system using an adaptive processor interface port (“APIP”) added to, or in conjunction with, the memory and I/O controller chip of the core logic. Memory accesses to and from this port, as well as the main microprocessor bus, are then arbitrated by the memory control circuitry forming a portion of the controller chip. In this fashion, both the microprocessors and the adaptive processors of the hybrid computing system exhibit equal memory bandwidth and latency. In addition, because it is a separate electrical port from the microprocessor bus, the APIP is not required to comply with, and participate in, all FSB protocol. This results in reduced protocol overhead which results higher yielded payload on the interface.

5. 发明申请

US20120117318A1 HETEROGENEOUS COMPUTING SYSTEM COMPRISING A SWITCH/NETWORK ADAPTER PORT INTERFACE UTILIZING LOAD-REDUCED DUAL IN-LINE MEMORY MODULES (LR-DIMMS) INCORPORATING ISOLATION MEMORY BUFFERS 审中-公开
标题翻译：包含开关/网络适配器端口接口的异构计算系统利用负载减少的双向在线存储器模块（LR-DIMMS）并入隔离存储器缓冲器
公开(公告)号：US20120117318A1
公开(公告)日：2012-05-10
申请号：US13286996
申请日：2011-11-01
申请人： Lee A. Burton , Thomas R. Seeman , Jon M. Huppenthal
发明人： Lee A. Burton , Thomas R. Seeman , Jon M. Huppenthal
IPC分类号： G06F12/00
CPC分类号： G06F13/1663
摘要： A heterogeneous computing system comprising a switch/network adapter port interface utilizing load-reduced dual in-line memory modules (LR-DIMMs) incorporating isolation memory buffers. In a particular embodiment of the present invention the computer system comprises at least one dense logic device and a controller coupling it to a memory bus. A plurality of memory slots are coupled to the memory bus and an adaptor port is associated with some number of the plurality of memory slots, each of the adapter ports including associated memory resources. A direct execution logic element is coupled to at least one of the adapter ports. The memory resources are selectively accessible by the at least one dense logic device and the direct execution logic element.
摘要翻译：异构计算系统包括利用负载减少的双列直插存储器模块（LR-DIMM）并入隔离存储器缓冲器的交换机/网络适配器端口接口。在本发明的特定实施例中，计算机系统包括至少一个密集逻辑设备和将其耦合到存储器总线的控制器。多个存储器插槽耦合到存储器总线，并且适配器端口与若干数量的多个存储器插槽相关联，每个适配器端口包括相关联的存储器资源。直接执行逻辑元件耦合到至少一个适配器端口。存储器资源可由至少一个密集逻辑器件和直接执行逻辑元件选择性地访问。

6. 发明授权

US07680968B2 Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module format (FB-DIMM) 有权
标题翻译：交换机/网络适配器端口包含可由直接执行逻辑元件和一个或多个密集逻辑设备以完全缓冲的双列直插存储器模块格式（FB-DIMM）选择性地访问的共享存储器资源，
公开(公告)号：US07680968B2
公开(公告)日：2010-03-16
申请号：US11834439
申请日：2007-08-06
申请人： Lee A. Burton
发明人： Lee A. Burton
IPC分类号： G06F13/12
CPC分类号： G06F13/385 , G06F13/1668
摘要： An enhanced switch/network adapter port incorporating shared memory resources (“SNAPM™”) selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module (“FB-DIMM”) format for clustered computing systems employing direct execution logic such as multi-adaptive processor elements (“MAP®”, all trademarks of SRC Computers, Inc.). Functionally, the SNAPM modules incorporate and properly allocate memory resources so that the memory appears to the associated dense logic device(s) (e.g. a microprocessor) to be functionally like any other system memory such that no time penalties are incurred when accessing it. Through the use of a programmable access coordination mechanism, the control of this memory can be handed off to the SNAPM memory controller and, once in control, the controller can move data between the shared memory resources and the computer network such that the transfer is performed at the maximum rate that the memory devices themselves can sustain. This provides the highest performance link to the other network devices such as MAP® elements, common memory boards and the like.
摘要翻译：增强的交换机/网络适配器端口，其包含可由直接执行逻辑元件和完全缓冲双列直插存储器模块（“FB-DIMM”）格式中的一个或多个密集逻辑设备可选择地共享存储器资源（“SNAPM TM”）对于采用诸如多自适应处理器元件（“MAP”“SRC Computers，Inc.的所有商标”）的直接执行逻辑的集群计算系统。在功能上，SNAPM模块并入并正确地分配存储器资源，使得相关联的密集逻辑设备（例如微处理器）的存储器在功能上与任何其他系统存储器一样，使得在访问时不会引起时间惩罚。通过使用可编程访问协调机制，可以将该存储器的控制权交给SNAPM存储器控制器，一旦控制，控制器可以在共享存储器资源和计算机网络之间移动数据，从而执行传输以存储器件本身可以承受的最大速率。这提供了与其他网络设备（如MAP®元件，公共存储器板等）的最高性能链接。

7. 发明授权

US07197575B2 Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers 有权
标题翻译：交换机/网络适配器端口将可重配置处理元件耦合到一个或多个微处理器以与交错存储器控制器一起使用
公开(公告)号：US07197575B2
公开(公告)日：2007-03-27
申请号：US10340390
申请日：2003-01-10
申请人： Jon M. Huppenthal , Thomas R. Seeman , Lee A. Burton
发明人： Jon M. Huppenthal , Thomas R. Seeman , Lee A. Burton
IPC分类号： G06F15/16
CPC分类号： G06F13/1663 , G06F13/1684
摘要： A switch/network adapter port (“SNAP™”) in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format for clustered computers employing multi-adaptive processor (“MAP®”, both trademarks of SRC Computers, Inc.) elements for use with interleaved memory controllers. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format adapter port coupled to a reconfigurable processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (“FPGA”) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.
摘要翻译：双串行内存模块（“DIMM”）或Rambus（TM）在线内存模块（“RIMM”）格式的交换机/网络适配器端口（“SNAP（TM）”），用于采用多自适应处理器（“MAP（R）”，SRC Computers，Inc.的两个商标）用于交错存储器控制器的元件。特别公开的是基于微处理器的计算机系统，其利用耦合到可重构处理器元件的DIMM或RIMM物理格式适配器端口来实现到外部交换机，网络或其他设备的连接。在特定实施例中，连接可以被提供给PCI，加速图形端口（“AGP”）或系统维护（“SM”）总线，用于将控制信息传递到主微处理器或其他控制芯片。基于现场可编程门阵列（“FPGA”）的处理元件具有将数据传送到外部互连结构或设备的能力。

8. 发明授权

US06996656B2 System and method for providing an arbitrated memory bus in a hybrid computing system 有权
标题翻译：在混合计算系统中提供仲裁的存储器总线的系统和方法
公开(公告)号：US06996656B2
公开(公告)日：2006-02-07
申请号：US10284994
申请日：2002-10-31
申请人： Lee A. Burton
发明人： Lee A. Burton
IPC分类号： G06F13/36 , G06F13/14 , G06F12/00
CPC分类号： G06F13/1663 , G06F13/1605 , G06F13/4031
摘要： A computing system having at least one microprocessor and a memory subsystem coupled to the at least one microprocessor. A memory controller is coupled to manage memory transactions between the memory subsystem and the at least one microprocessor. At least one arbitration port is coupled to the memory controller and configured to receive an external arbitration signal.
摘要翻译：具有至少一个微处理器和耦合到所述至少一个微处理器的存储器子系统的计算系统。存储器控制器被耦合以管理存储器子系统和至少一个微处理器之间的存储器事务。至少一个仲裁端口耦合到存储器控制器并且被配置为接收外部仲裁信号。

9. 发明授权

US06295598B1 Split directory-based cache coherency technique for a multi-processor computer system 失效
标题翻译：用于多处理器计算机系统的基于目录的高速缓存一致性技术
公开(公告)号：US06295598B1
公开(公告)日：2001-09-25
申请号：US09108088
申请日：1998-06-30
申请人： Jonathan L. Bertoni , Lee A. Burton
发明人： Jonathan L. Bertoni , Lee A. Burton
IPC分类号： G06F930
CPC分类号： G06F12/0826
摘要： A split directory-based cache coherency technique utilizes a secondary directory in memory to implement a bit mask used to indicate when more than one processor cache in a multi-processor computer system contains the same line of memory which thereby reduces the searches required to perform the coherency operations and the overall size of the memory needed to support the coherency system. The technique includes the attachment of a “coherency tag” to a line of memory so that its status can be tracked without having to read each processor's cache to see if the line of memory is contained within that cache. In this manner, only relatively short cache coherency commands need be transmitted across the communication network (which may comprise a Sebring ring) instead of across the main data path bus thus freeing the main bus from being slowed down by cache coherency data transmissions while removing the bandwidth limitations inherent in other cache coherency techniques. The technique disclosed may be further expanded to incorporate the “bus lock” capability of bus-based systems compatible with the requirements for multi-processor synchronization.
摘要翻译：基于分割目录的高速缓存一致性技术利用存储器中的次目录来实现位掩码，用于指示多处理器计算机系统中的多于一个处理器高速缓存何时包含相同的存储器行，从而减少了执行一致性操作和支持一致性系统所需的内存的总体大小。该技术包括将“相干性标签”附加到存储器行，使得可以跟踪其状态而不必读取每个处理器的高速缓存以查看该存储器行是否包含在该高速缓存内。以这种方式，仅需要相对较短的缓存一致性命令才能跨越通信网络（其可以包括塞布林环）而不是跨主数据路径总线传送，从而使主总线免受高速缓存一致性数据传输的减慢，同时移除其他高速缓存一致性技术固有的带宽限制。所公开的技术可以进一步扩展，以结合与多处理器同步的要求兼容的基于总线的系统的“总线锁定”能力。

10. 发明授权

US07421524B2 Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format 有权
公开(公告)号：US07421524B2
公开(公告)日：2008-09-02
申请号：US10996016
申请日：2004-11-23
申请人： Jon M. Huppenthal , Thomas R. Seeman , Lee A. Burton
发明人： Jon M. Huppenthal , Thomas R. Seeman , Lee A. Burton
IPC分类号： G06F13/12
CPC分类号： G06F15/7867 , G06F13/4027
摘要： A switch/network adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to significantly enhance data transfer rates over that otherwise available through use of the standard peripheral component interconnect (“PCI”) bus. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (“FPGA”) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.

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