专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07987391B2 Fault tolerance using digests 有权
标题翻译：使用摘要的容错
公开(公告)号：US07987391B2
公开(公告)日：2011-07-26
申请号：US10392698
申请日：2003-03-20
申请人： Lawrence Butcher
发明人： Lawrence Butcher
IPC分类号： G06F11/00
CPC分类号： G06F11/1482 , G06F11/1641 , G06F11/165 , G06F11/184
摘要： A method and apparatus are provided, the method and apparatus comprising running a plurality of identical programs on a plurality of identical computers and recording information about at least some state updates done within each of the plurality of the identical programs running on the plurality of the identical computers using a plurality of digests of the at least some state updates. The method and apparatus also comprises comparing the plurality of the digests to determine whether at least one of the plurality of the identical programs running on the plurality of the identical computers has failed.
摘要翻译：提供了一种方法和装置，所述方法和装置包括在多个相同的计算机上运行多个相同的程序，并且记录关于在多个相同的计算机上运行的多个相同程序中的每一个内完成的至少一些状态更新的信息使用至少一些状态更新的多个摘要的计算机。所述方法和装置还包括比较多个摘要以确定在多个相同的计算机上运行的多个相同程序中的至少一个是否已经失败。

2. 发明授权

US06993617B2 System-on-a-chip having an on-chip processor and an on-chip dynamic random access memory (DRAM) 有权
公开(公告)号：US06993617B2
公开(公告)日：2006-01-31
申请号：US10393865
申请日：2003-03-21
申请人： Lawrence Butcher , Duane Northcutt , Marc Schneider , Jerry Wall , James Hanko , Alan Ruberg , Satyanarayana Simha , Michael E. Duboce , Arvind Srinivasan
发明人： Lawrence Butcher , Duane Northcutt , Marc Schneider , Jerry Wall , James Hanko , Alan Ruberg , Satyanarayana Simha , Michael E. Duboce , Arvind Srinivasan
IPC分类号： G06F13/00 , G06F13/38 , G06F13/40
CPC分类号： G06F15/786 , G06F15/7842
摘要： A system-on-a-chip device is provided, the system-on-a-chip device comprising an on-chip processor and an on-chip dynamic random access memory (DRAM) capable of communicating with the on-chip processor. The system-on-a-chip device also comprises at least one on-chip input/output (I/O) bus capable of communicating with the on-chip processor and the on-chip dynamic random access memory (DRAM).

3. 发明申请

US20090013095A1 OPERATION OF MEDIA INTERFACE TO PROVIDE BIDIRECTIONAL COMMUNICATIONS 有权
标题翻译：媒体接口的操作提供双向通信
公开(公告)号：US20090013095A1
公开(公告)日：2009-01-08
申请号：US12147248
申请日：2008-06-26
申请人： Lawrence Butcher
发明人： Lawrence Butcher
IPC分类号： G06F3/01
CPC分类号： H04N5/765 , H04L12/2832 , H04N5/77 , H04N5/775 , H04N21/43615 , H04N21/43632
摘要： Embodiments of the invention are generally directed to operation of a media interface to provide bidirectional communications. An embodiment of a method includes connecting a first device to a second device via a media interface, the media interface including a communication channels for unidirectional data transmission, the media interface being in compliance with a media protocol. The method further provides for configuring the first device and the second device for bidirectional data transmission, the bidirectional data transmission being conducted according to a network protocol, and transmitting bidirectional data between the first device and the second device via the media interface.
摘要翻译：本发明的实施例通常涉及媒体接口的操作以提供双向通信。方法的实施例包括经由媒体接口将第一设备连接到第二设备，媒体接口包括用于单向数据传输的通信信道，媒体接口符合媒体协议。该方法还提供用于配置用于双向数据传输的第一设备和第二设备，根据网络协议进行双向数据传输，以及经由介质接口在第一设备和第二设备之间传送双向数据。

4. 发明申请

US20070260965A1 Error detection in physical interfaces for point-to-point communications between integrated circuits 有权
标题翻译：集成电路之间点对点通信的物理接口中的错误检测
公开(公告)号：US20070260965A1
公开(公告)日：2007-11-08
申请号：US11372866
申请日：2006-03-09
申请人： Brian Schmidt , Lawrence Butcher
发明人： Brian Schmidt , Lawrence Butcher
IPC分类号： H04L1/00
CPC分类号： H04L1/0045 , H04L1/0061 , H04L25/4908 , H04L2001/0092
摘要： An apparatus, system and method for detecting errors in a physical interface during the transmission and/or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, an apparatus is configured to operate as or within a receiving physical interface. The apparatus includes a decoder configured to decode a subset of encoded data bits to yield decoded data bits. It also includes a physical interface (“PI”) error detection bit extractor configured to extract a physical interface error detection bit from the decoded data bits. As such, the apparatus uses the physical interface error detection bit to determine whether the encoded data bits include at least one erroneous data bit as an error. In some embodiments, the apparatus includes an error detector configured to operate within a physical layer. In at least one embodiment, the apparatus efficiently transmits error detection codes within, for example, an NB/(N+1)B line coder.
摘要翻译：公开了在集成电路（“IC”）之间的数据通信传输和/或接收期间检测物理接口中的错误的装置，系统和方法。在一个实施例中，设备被配置为在接收物理接口内或内部进行操作。该装置包括解码器，其被配置为解码编码数据位的子集以产生解码的数据位。它还包括物理接口（“PI”）错误检测位提取器，用于从解码的数据位提取物理接口错误检测位。这样，该装置使用物理接口错误检测位来确定编码数据位是否包括至少一个错误数据位作为错误。在一些实施例中，该装置包括被配置为在物理层内操作的错误检测器。在至少一个实施例中，该装置在例如NB /（N + 1）B线路编码器内有效地发送错误检测码。

5. 发明授权

US06952810B2 Coding speed and correctness of hardware description language (HDL) descriptions of hardware 有权
标题翻译：硬件描述语言（HDL）硬件描述的编码速度和正确性
公开(公告)号：US06952810B2
公开(公告)日：2005-10-04
申请号：US10413280
申请日：2003-04-14
申请人： Lawrence Butcher , Krutibas Biswal , Arvind Srinivasan
发明人： Lawrence Butcher , Krutibas Biswal , Arvind Srinivasan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method is provided, the method comprising collecting related signals capable of having unrelated names into a Krutibus, defining a bus capable of connecting the related signals in a bus definition file in the Krutibus and providing at least one of component declarations of the bus and different uses of the bus in a hardware description language (HDL) circuit description using the bus definition file in the Krutibus. The method also comprises providing a Krutibus preprocessor to read the hardware description language (HDL) circuit description for the at least one of the component declarations of the bus and the different uses of the bus and to generate a hardware description language (HDL) circuit description naming the bus components.
摘要翻译：提供了一种方法，该方法包括收集能够将无关名称的相关信号收集到Krutibus中，定义能够连接Krutibus中的总线定义文件中的相关信号的总线，并提供总线的分量声明和不同的组件声明中的至少一个使用总线在硬件描述语言（HDL）电路描述中使用总线定义文件在Krutibus。该方法还包括提供一个Krutibus预处理器来读取总线的组件声明中的至少一个的总线的硬件描述语言（HDL）电路描述和总线的不同用途，并且生成硬件描述语言（HDL）电路描述命名总线组件。

6. 发明授权

US5581269A Method of use of multiple input styli in a system of multiple computers 失效
标题翻译：在多台计算机系统中使用多种输入触笔的方法
公开(公告)号：US5581269A
公开(公告)日：1996-12-03
申请号：US340139
申请日：1994-11-15
申请人： Lawrence Butcher
发明人： Lawrence Butcher
IPC分类号： G06F3/038 , G06F3/041 , G09G5/00
CPC分类号： G06F3/038
摘要： In a system of multiple computers connected by a network means, a method for using multiple input styli, each connected to an individual computer, to indicate input information on the display screen of any computer in the system. In a system in which there are many computers, a user of one computer may wish to indicate an input action on a second computer. In the present invention, all pens in a system are able to determine which computer they are writing on and an input position relative to that input computer, regardless of whether they belong to that computer, by determining an identifying "signature" of the computer based on the peak signal strength of a plurality of distinguishable signals in a complex signal produced on the computer display screen and sensed by the stylus. Each stylus is able to communicate with the software entity which can correctly interpret the measurement by using a computer network.
摘要翻译：在通过网络装置连接的多台计算机的系统中，使用多个输入测针的方法，每个连接到单个计算机，以在系统中的任何计算机的显示屏上指示输入信息。在其中有许多计算机的系统中，一台计算机的用户可能希望在第二计算机上指示输入动作。在本发明中，系统中的所有笔都能够通过确定基于计算机的识别“签名”来确定他们正在写入哪个计算机以及相对于该输入计算机的输入位置，而不管它们是否属于该计算机关于在计算机显示屏幕上产生并由触笔感测的复合信号中的多个可区分信号的峰值信号强度。每个触控笔能够与软件实体进行通信，软件实体可以通过使用计算机网络来正确解释测量。

7. 发明授权

US07216248B2 On-chip clock generator allowing rapid changes of on-chip clock frequency 有权
标题翻译：片上时钟发生器允许片上时钟频率快速变化
公开(公告)号：US07216248B2
公开(公告)日：2007-05-08
申请号：US10393229
申请日：2003-03-20
申请人： Lawrence Butcher
发明人： Lawrence Butcher
IPC分类号： G06F1/00
CPC分类号： G06F1/08
摘要： A method and apparatus are provided, the method and apparatus comprising sending an output of a free-running counter to a comparator for a clock shaper logic unit, the free-running counter incremented every time a double-speed clock rises for an on-chip system and sending at least one input from a central processing unit (CPU) to the comparator for the clock shaper logic unit, the at least one input specifying a desired frequency. The method and apparatus also comprises producing a central processing unit (CPU) clock in the clock shaper logic unit based on the output of the free-running counter and the at least one input specifying the desired frequency by comparing a bit-reversed version of the output of the free-running counter with the at least one input specifying the desired frequency.
摘要翻译：提供了一种方法和装置，所述方法和装置包括向时钟整形器逻辑单元的比较器发送自由运行计数器的输出，每当双倍速时钟上升时，自由运行计数器递增系统，并且将来自中央处理单元（CPU）的至少一个输入发送到时钟整形器逻辑单元的比较器，所述至少一个输入指定期望的频率。该方法和装置还包括基于自由运行计数器的输出和指定所需频率的至少一个输入，在时钟整形器逻辑单元中产生中央处理单元（CPU）时钟，自动运行计数器的输出与至少一个指定期望频率的输入。

8. 发明授权

US06438141B1 Method and management of communications over media of finite bandwidth 失效
标题翻译：有限带宽媒体通信方法与管理
公开(公告)号：US06438141B1
公开(公告)日：2002-08-20
申请号：US09063491
申请日：1998-04-20
申请人： James Hanko , Jerry Wall , Duane Northcutt , Lawrence Butcher , Alan T. Ruberg , Herbert Bos
发明人： James Hanko , Jerry Wall , Duane Northcutt , Lawrence Butcher , Alan T. Ruberg , Herbert Bos
IPC分类号： H04J318
CPC分类号： H04L47/822 , H04J3/1682 , H04L47/70 , H04L47/745 , H04L47/823
摘要： The invention provides a method and apparatus for management of communications over media of finite bandwidth. One embodiment of the invention allows management of communications comprising a plurality of data streams from a plurality of sources. One embodiment of the invention effectively quantifies and controls data streams comprising data transferred at either regular or irregular data rates. One embodiment of the invention provides for estimation of data rate needs, measurement and analysis of current and historical data rate parameters, dynamic allocation of available bandwidth, and supports cooperation between data sources and destinations in the management processes.
摘要翻译：本发明提供一种用于管理有限带宽介质上的通信的方法和装置。本发明的一个实施例允许管理包括来自多个源的多个数据流的通信。本发明的一个实施例有效地量化和控制包括以规则或不规则数据速率传送的数据的数据流。本发明的一个实施例提供对数据速率需求的估计，当前和历史数据速率参数的测量和分析，可用带宽的动态分配，以及支持管理过程中数据源和目的地之间的协作。

9. 发明授权

US5437057A Wireless communications using near field coupling 失效
标题翻译：使用近场耦合的无线通信
公开(公告)号：US5437057A
公开(公告)日：1995-07-25
申请号：US984821
申请日：1992-12-03
申请人： Edward A. Richley , Lawrence Butcher
发明人： Edward A. Richley , Lawrence Butcher
IPC分类号： H04B7/26 , H04B5/00 , H04B5/02 , H04L12/28 , H04Q7/22 , H04Q7/28
CPC分类号： H04B5/0012 , H04B5/02
摘要： Near field coupling is employed for transferring data back and forth between base stations and portable stations in cellular communication systems, such as cellular local area networks.
摘要翻译：近场耦合用于在诸如蜂窝局域网的蜂窝通信系统中的基站和便携式站之间来回传送数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式