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1. 发明授权

US06595633B2 Printer pen carriage support 有权
公开(公告)号：US06595633B2
公开(公告)日：2003-07-22
申请号：US10021957
申请日：2001-12-14
申请人： Charles F. McCord, Jr. , Laura E. Simmons
发明人： Charles F. McCord, Jr. , Laura E. Simmons
IPC分类号： B41J2300
CPC分类号： B41J2/1752
摘要： A printer pen carriage support for a printer is disclosed. The printer pen carriage support includes a cantilever that fits within a groove of a pen carriage and provides support for the pen carriage. Support structures, such as bushings or bearings, may be included to assist in pen carriage movement along the cantilever.

2. 发明授权

US5493242A Status register with asynchronous read and reset and method for providing same 失效
标题翻译：具有异步读取和复位的状态寄存器和提供相同的方法
公开(公告)号：US5493242A
公开(公告)日：1996-02-20
申请号：US86339
申请日：1993-06-30
申请人： Laura E. Simmons , Joseph A. Thomsen
发明人： Laura E. Simmons , Joseph A. Thomsen
IPC分类号： G01R31/3185 , G06F11/00 , G06F11/16 , G06F11/22 , G11C7/10 , H03K5/22
CPC分类号： G06F11/167 , G06F11/0751 , G11C7/1051 , G11C7/1078 , G01R31/31858 , G06F11/2205
摘要： A single bit status register includes an input flip-flop, an asynchronous latch having an input coupled to an output of the input flip-flop, a comparator for comparing the outputs of the flip-flop and the latch, and an output stage which provides an error output when the comparator determines that the outputs of the flip-flop and the latch are not the same. In this fashion, it is known when a "read" of the status register is invalid due to the presence of the error output. Preferably, the register also includes a reset disabling mechanism which prevents the input flip-flop from being reset until a valid read has occurred. A n-bit status register includes n register sections, where each register section includes an input flip-flop, an asynchronous latch having an input coupled to an output of the input flip-flop, and a register section comparison mechanism for comparing the outputs of the flip-flop and the latch in that register section. The method of the present invention includes the steps of: a) capturing a status bit in an input flip; b) latching the status bit into an output latch; c) asynchronously enabling the output latch; d) comparing the outputs of the flip-flop and the latch; e) outputting an error signal if the outputs of the flip-flop and the latch are different; and f) outputting the status bit at least if the output of the flip-flop and the latch are the same.
摘要翻译：单位状态寄存器包括输入触发器，具有耦合到输入触发器的输出的输入的异步锁存器，用于比较触发器和锁存器的输出的比较器和提供当比较器确定触发器和锁存器的输出不相同时的误差输出。以这种方式，由于存在错误输出，状态寄存器的“读”是无效的。优选地，寄存器还包括复位禁止机制，其防止输入触发器被复位，直到发生有效的读取。 n位状态寄存器包括n个寄存器部分，其中每个寄存器部分包括输入触发器，具有耦合到输入触发器的输出的输入的异步锁存器，以及一个寄存器部分比较机构，该触发器和该寄存器部分中的锁存器。本发明的方法包括以下步骤：a）捕获输入翻转中的状态位; b）将状态位锁定到输出锁存器中; c）异步地使能输出锁存器; d）比较触发器和锁存器的输出; e）如果触发器和闩锁的输出不同，则输出误差信号; 以及f）至少如果所述触发器和所述锁存器的输出相同，则输出所述状态位。

3. 发明授权

US06931259B2 Integrated circuit architecture for programmable wireless device 有权
标题翻译：用于可编程无线设备的集成电路架构
公开(公告)号：US06931259B2
公开(公告)日：2005-08-16
申请号：US09969941
申请日：2001-10-02
申请人： Laura E Simmons , James Daren Bledsoe , Daniel I Croft , Patrick A. McKinley , Gregory Frank Carlson , Ignacio Jose Perez , Paul Anthony Chenard , Raymond Jensen Hasler , Shelly Rose Reasoner , Todd Alan McClelland , Thomas P. Bruch
发明人： Laura E Simmons , James Daren Bledsoe , Daniel I Croft , Patrick A. McKinley , Gregory Frank Carlson , Ignacio Jose Perez , Paul Anthony Chenard , Raymond Jensen Hasler , Shelly Rose Reasoner , Todd Alan McClelland , Thomas P. Bruch
IPC分类号： H04B1/38 , H04L12/28 , H04L12/56 , H04M1/725 , H04M1/00
CPC分类号： H04M1/72527 , H04W88/02 , H04W88/04
摘要： The present invention is an integrated system on a chip that combines wireless, graphics, and multimedia. The graphics and multimedia features may be programmed by the end user while restricting programmability of the wireless features.
摘要翻译：本发明是组合无线，图形和多媒体的芯片上的集成系统。图形和多媒体功能可以由最终用户编程，同时限制无线功能的可编程性。

4. 发明授权

US06561618B1 Service station for printers having firing nozzles perpendicular to direction of carriage motion 有权
公开(公告)号：US06561618B1
公开(公告)日：2003-05-13
申请号：US09715628
申请日：2000-11-17
申请人： Laura E Simmons , Jonathan N Andrews , Stephen Vance Cooper
发明人： Laura E Simmons , Jonathan N Andrews , Stephen Vance Cooper
IPC分类号： B41J2165
CPC分类号： B41J23/025 , B41J2/16547
摘要： A thermal inkjet printer with firing nozzles perpendicular to the carriage motion has two motors: paper and carriage. These motors, alone or in concert, provide the power to the service station. The service station has separate wiping and pen cleaning functions. The wipers need to move across the pens in a direction that is perpendicular the carriage direction. Through the use of gears, the wipers can be made to clean the pens at the same time that the paper is being advanced and using the same motor source. For capping, the caps are moved into place as the pens come to rest. The motion of the pens themselves could easily push a lever that pushes the caps into place.

5. 发明授权

US5958055A Power management system for a computer 失效
标题翻译：电脑电源管理系统
公开(公告)号：US5958055A
公开(公告)日：1999-09-28
申请号：US717478
申请日：1996-09-20
申请人： David R. Evoy , Gary D. Hicok , Laura E. Simmons
发明人： David R. Evoy , Gary D. Hicok , Laura E. Simmons
IPC分类号： G06F1/32 , G06F11/00
CPC分类号： G06F1/3209 , G06F11/004
摘要： An off-hook state of a telephone associated with a computer is used in order to disable the power management unit of the computer to prevent premature power shutdown while the telephone is being used. A power-managed computer system includes a bus system, and a central processing unit coupled to the bus system. The central processing unit has a normal power mode and a power saving mode. A telephony interface coupled to the bus system has a port for coupling to a telephone system network. A power management unit is also coupled to the bus system and is responsive to bus system activity and to indicia of telephony interface activity. The power management unit causes the central processing unit to be in a power saving mode when both bus system activity and telephony interface activity are less than a predetermined level of activity. Additionally, the power management unit maintains the central processing unit in a power mode greater than the power saving mode when either the bus system activity or the telephony interface activity is greater than the predetermined level of activity. An off-hook signal is directly sampled from the modem and provided to activity detection logic within the power management unit. Alternatively, modem interface logic interprets any number of signals provided by the modem to deliver an off-hook signal to the power management unit. Alternatively, telephone interface software includes an off-hook identifier that records the off-hook state of the telephone and an enablement/disablement register in the power management unit is either set or reset. System or user activity is also emulated in order to indicate to the power management unit that activity is occurring within the computer.
摘要翻译：使用与计算机相关联的电话机的摘机状态，以便禁用计算机的电源管理单元以防止在使用电话时过早停电。功率管理的计算机系统包括总线系统和耦合到总线系统的中央处理单元。中央处理单元具有正常功率模式和省电模式。耦合到总线系统的电话接口具有用于耦合到电话系统网络的端口。电力管理单元还耦合到总线系统，并响应于总线系统活动和电话接口活动的标记。当总线系统活动和电话接口活动都小于预定活动水平时，电源管理单元使得中央处理单元处于省电模式。此外，当总线系统活动或电话接口活动大于预定活动水平时，电力管理单元将中央处理单元维持在大于省电模式的功率模式中。摘机信号从调制解调器直接采样并提供给电源管理单元内的活动检测逻辑。或者，调制解调器接口逻辑解释由调制解调器提供的任何数量的信号以将摘机信号传送到电力管理单元。或者，电话接口软件包括记录电话的摘机状态的摘机标识符，并且电源管理单元中的启用/禁用寄存器被设置或复位。系统或用户活动也被仿真，以向电力管理单元指示在计算机内发生的活动。

6. 发明授权

US5223751A Logic level shifter for 3 volt CMOS to 5 volt CMOS or TTL 失效
标题翻译：用于3伏CMOS到5伏CMOS或TTL的逻辑电平变换
公开(公告)号：US5223751A
公开(公告)日：1993-06-29
申请号：US780677
申请日：1991-10-29
申请人： Laura E. Simmons , Richard W. Ulmer , James Ward
发明人： Laura E. Simmons , Richard W. Ulmer , James Ward
IPC分类号： H03K19/00 , H03K19/0185
CPC分类号： H03K19/0013 , H03K19/018521
摘要： A logic level shifter characterized by a first inverting stage which shifts an input signal downwardly to a lower level, and a second inverting stage which shifts the lower level upwardly to an output signal level which is greater than the input signal level. Feedback from the output is used to virtually eliminate static current drain when the input logic level is 0. The method of the invention involves downwardly shifting an input range of voltages to a lower range of voltages, and then upwardly shifting the lower range of voltages to an output range of voltages which is greater than the input range of voltages. There is preferably a first inversion in the downward shift and a second inversion in the upward shift. A sensing step senses the output voltage to reduce the static current consumed by the process.
摘要翻译：一种逻辑电平移位器，其特征在于将输入信号向下移动到较低电平的第一反相级，以及向下移动较低电平至大于输入信号电平的输出信号电平的第二反相级。当输入逻辑电平为0时，来自输出的反馈用于实际消除静态电流消耗。本发明的方法涉及将输入范围的电压向下移位到较低的电压范围，然后向下移动较低的电压范围电压的输出范围大于电压的输入范围。优选地，向下移动中的第一反转和向上移位的第二反转。感测步骤检测输出电压以减少由该过程消耗的静态电流。

7. 发明授权

US5822548A Programming interface for a universal asynchronous receiver/transmitter 失效
标题翻译：通用异步接收机/发射机的编程接口
公开(公告)号：US5822548A
公开(公告)日：1998-10-13
申请号：US586040
申请日：1996-01-16
申请人： Franklyn H. Story , Scott E. Harrow , Laura E. Simmons
发明人： Franklyn H. Story , Scott E. Harrow , Laura E. Simmons
IPC分类号： G06F13/10 , H01J13/00
CPC分类号： G06F13/105
摘要： A universal asynchronous receiver/transmitter (UART) computer programming interface emulates three-wire interface control. A register select circuit is supplied with address signals from a host CPU and has a plurality of register outputs organized into first and second groups. One of these groups of outputs are those which are required for three-wire operation in communications devices; and these outputs are mapped to the appropriate communications devices or registers. The other group of outputs required for three-wire operation, but with no corresponding function in a communications device, are implemented by means of an UART emulator circuit producing a data output which is coupled to an internal data bus, along with the output of the registers for the communications devices.
摘要翻译：通用异步收发器（UART）计算机编程接口模拟三线接口控制。寄存器选择电路被提供有来自主机CPU的地址信号，并且具有组织成第一和第二组的多个寄存器输出。这些输出组之一是通信设备中三线操作所需的输出; 并将这些输出映射到适当的通信设备或寄存器。在通信设备中三线操作所需的另一组输出，通过UART仿真器电路来实现，该仿真器电路产生耦合到内部数据总线的数据输出，连同输出的注册通信设备。

8. 再颁专利

USRE36839E Method and apparatus for reducing power consumption in digital electronic circuits 有权
标题翻译：用于降低数字电子电路功耗的方法和装置
公开(公告)号：USRE36839E
公开(公告)日：2000-08-29
申请号：US212854
申请日：1998-12-16
申请人： Laura E. Simmons , Rajeev Jayavant
发明人： Laura E. Simmons , Rajeev Jayavant
IPC分类号： G06F1/32 , H03K19/096 , H03K19/00
CPC分类号： G06F1/3287 , G06F1/3203 , Y02B60/1282 , Y02B60/32
摘要： An integrated circuit with power conservation includes a number of functional blocks, each of which includes a digital circuitry and at least one output control line, and a power controller coupled to the control lines. The output control lines develop clock control signals based upon a functional block's knowledge of the direction of data flow. The power controller the reduces power by deactivating functional blocks that are not needed as indicated by the clock control signals. More specifically, a system with power conservation includes a number of functional blocks capable of processing data, each of the functional blocks including a modulated clock input and N+1 clock control lines which reflect the direction of data flow, where N is a number of neighbors of a particular functional block, and a clock controller having an input clock, the clock controller being coupled to the modulated clock inputs and the clock control lines of the functional blocks. The clock controller is operative to modulate the input clock in accordance with the signals on the clock control lines to provide modulated clocks to each of the plurality of functional blocks. A method for reducing power consumption includes the steps of: a) receiving control signals from a number of functional blocks; b) selectively deactivating a particular functional block upon a request from that functional block or from another functional block; and c) activating the particular functional block upon a request from another functional block.
摘要翻译：具有功率节省的集成电路包括多个功能块，每个功能块包括数字电路和至少一个输出控制线，以及耦合到控制线的功率控制器。输出控制线根据功能块对数据流方向的了解，开发时钟控制信号。功率控制器通过停用时钟控制信号所指示的不需要的功能块来降低功耗。更具体地说，具有省能的系统包括能够处理数据的多个功能块，每个功能块包括调制时钟输入和反映数据流的方向的N + 1个时钟控制线，其中N是特定功能块的邻居以及具有输入时钟的时钟控制器，所述时钟控制器耦合到调制时钟输入和功能块的时钟控制线。时钟控制器可操作以根据时钟控制线上的信号调制输入时钟，以向多个功能块中的每一个提供调制时钟。一种降低功耗的方法包括以下步骤：a）从多个功能块接收控制信号; b）根据来自该功能块或另一功能块的请求选择性地去激活特定功能块; 以及c）在来自另一功能块的请求时激活所述特定功能块。

9. 发明授权

US5596288A Status register with asynchronous read and reset and method for providing same 失效
标题翻译：具有异步读取和复位的状态寄存器和提供相同的方法
公开(公告)号：US5596288A
公开(公告)日：1997-01-21
申请号：US526119
申请日：1995-09-07
申请人： Laura E. Simmons , Joseph A. Thomsen
发明人： Laura E. Simmons , Joseph A. Thomsen
IPC分类号： G01R31/3185 , G06F11/00 , G06F11/16 , G06F11/22 , G11C7/10 , H03K5/22
CPC分类号： G06F11/167 , G06F11/0751 , G11C7/1051 , G11C7/1078 , G01R31/31858 , G06F11/2205
摘要： A single bit status register includes an input flip-flop, an asynchronous latch having an input coupled to an output of the input flip-flop, a comparator for comparing the outputs of the flip-flop and the latch, and an output stage which provides an error output when the comparator determines that the outputs of the flip-flop and the latch are not the same. In this fashion, it is known when a "read" of the status register is invalid due to the presence of the error output. Preferably, the register also includes a reset disabling mechanism which prevents the input flip-flop from being reset until a valid read has occurred. A n-bit status register includes n register sections, where each register section includes an input flip-flop, an asynchronous latch having an input coupled to an output of the input flip-flop, and a register section comparison mechanism for comparing the outputs of the flip-flop and the latch in that register section. The method of the present invention includes the steps of: a) capturing a status bit in an input flip; b) latching the status bit into an output latch; c) asynchronously enabling the output latch; d) comparing the outputs of the flip-flop and the latch; e) outputting an error signal if the outputs of the flip-flop and the latch are different; and f) outputting the status bit at least if the output of the flip-flop and the latch are the same.
摘要翻译：单位状态寄存器包括输入触发器，具有耦合到输入触发器的输出的输入的异步锁存器，用于比较触发器和锁存器的输出的比较器和提供当比较器确定触发器和锁存器的输出不相同时的误差输出。以这种方式，由于存在错误输出，状态寄存器的“读”是无效的。优选地，寄存器还包括复位禁止机制，其防止输入触发器被复位，直到发生有效的读取。 n位状态寄存器包括n个寄存器部分，其中每个寄存器部分包括输入触发器，具有耦合到输入触发器的输出的输入的异步锁存器，以及一个寄存器部分比较机构，触发器和该寄存器部分中的锁存器。本发明的方法包括以下步骤：a）捕获输入翻转中的状态位; b）将状态位锁定到输出锁存器中; c）异步地使能输出锁存器; d）比较触发器和锁存器的输出; e）如果触发器和闩锁的输出不同，则输出误差信号; 以及f）至少如果所述触发器和所述锁存器的输出相同，则输出所述状态位。

10. 发明授权

US5585745A Method and apparatus for reducing power consumption in digital electronic circuits 失效
标题翻译：用于降低数字电子电路功耗的方法和装置
公开(公告)号：US5585745A
公开(公告)日：1996-12-17
申请号：US686272
申请日：1996-07-25
申请人： Laura E. Simmons , Rajeev Jayavant
发明人： Laura E. Simmons , Rajeev Jayavant
IPC分类号： G06F1/32 , H03K19/096 , H03K19/00
CPC分类号： G06F1/3287 , G06F1/3203 , Y02B60/1282 , Y02B60/32
摘要： An integrated circuit with power conservation includes a number of functional blocks, each of which includes digital circuitry and at least one output control line, and a power controller coupled to the control lines. The output control lines develop clock control signals based upon a functional block's knowledge of the direction of data flow. The power controller the reduces power by deactivating functional blocks that are not needed as indicated by the clock control signals. More specifically, a system with power conservation includes a number of functional blocks capable of processing data, each of the functional blocks including a modulated clock input and N+1 clock control lines which reflect the direction of data flow, where N is a number of neighbors of a particular functional block, and a clock controller having an input clock, the clock controller being coupled to the modulated clock inputs and the clock control lines of the functional blocks. The clock controller is operative to modulate the input clock in accordance with the signals on the clock control lines to provide modulated clocks to each of the plurality of functional blocks. A method for reducing power consumption includes the steps of: a) receiving control signals from a number of functional blocks; b) selectively deactivating a particular functional block upon a request from that functional block or from another functional block; and c) activating the particular functional block upon a request from another functional block.
摘要翻译：具有功率保存的集成电路包括多个功能块，每个功能块包括数字电路和至少一个输出控制线，以及耦合到控制线的功率控制器。输出控制线根据功能块对数据流方向的了解，开发时钟控制信号。功率控制器通过停用时钟控制信号所指示的不需要的功能块来降低功耗。更具体地说，具有省能的系统包括能够处理数据的多个功能块，每个功能块包括调制时钟输入和反映数据流的方向的N + 1个时钟控制线，其中N是特定功能块的邻居以及具有输入时钟的时钟控制器，所述时钟控制器耦合到调制时钟输入和功能块的时钟控制线。时钟控制器可操作以根据时钟控制线上的信号调制输入时钟，以向多个功能块中的每一个提供调制时钟。一种降低功耗的方法包括以下步骤：a）从多个功能块接收控制信号; b）根据来自该功能块或另一功能块的请求选择性地去激活特定功能块; 以及c）在来自另一功能块的请求时激活所述特定功能块。

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