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1. 发明授权

US5651110A Apparatus and method for controlling data flow between a computer and memory devices 失效
标题翻译：用于控制计算机和存储设备之间的数据流的装置和方法
公开(公告)号：US5651110A
公开(公告)日：1997-07-22
申请号：US422005
申请日：1995-04-12
申请人： David T. Powers , David H. Jaffe , Larry P. Henson , Hoke S. Johnson, III , Joseph S. Glider , Thomas E. Idleman
发明人： David T. Powers , David H. Jaffe , Larry P. Henson , Hoke S. Johnson, III , Joseph S. Glider , Thomas E. Idleman
IPC分类号： G06F11/00 , G06F11/10 , G06F11/20 , G11B20/18 , G06F13/14
CPC分类号： G06F11/2092 , G06F11/1076 , G11B20/1833 , G06F11/0757 , G06F11/2033
摘要： A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remains constant. The invention also includes switching circuitry which permits a functioning second level controller to assume control of a group of memory devices formerly primarily controlled by the failed second level controller.
摘要翻译：一种用于控制计算机和以特定逻辑配置排列的一组存储器件之间的数据流的方法和装置。该系统包括一组第一级控制器和一组二级控制器。第一级控制器和第二级控制器协同工作，使得如果第二级控制器之一发生故障，则将第一级控制器与存储设备之间的路由切换到正常运行的第二级控制器，而无需使计算机进入重新路由过程。存储器件的逻辑配置保持不变。本发明还包括切换电路，其允许正常工作的第二电平控制器控制先前由故障的第二电平控制器控制的一组存储器装置。

2. 发明授权

US5414818A Method and apparatus for controlling reselection of a bus by overriding a prioritization protocol 失效
标题翻译：通过重写优先级协议来控制总线重选的方法和装置
公开(公告)号：US5414818A
公开(公告)日：1995-05-09
申请号：US505746
申请日：1990-04-06
申请人： Larry P. Henson , Kumar Gajjar , Thomas E. Idleman
发明人： Larry P. Henson , Kumar Gajjar , Thomas E. Idleman
IPC分类号： G06F13/36 , G06F13/374 , G06F13/42
CPC分类号： G06F13/374 , G06F13/36
摘要： The present invention provides a method and apparatus for dynamically modifying the priority of access to a bus, where the bus has control and arbitration functions distributed among the devices coupled to the bus, with each device having a fixed priority level. Access to the bus by particular devices is selectively inhibited, preventing them from asserting their fixed priority level. In a preferred embodiment, the present invention provides control over the reselection of a SCSI bus by a plurality of SCSI devices coupled to the bus by providing a pseudo busy signal to SCSI devices from which reselection is not desired. In this fashion, an initiator may issue a plurality of commands to the SCSI devices and control the order in which the devices will be serviced when ready. A plurality of pseudo busy circuits are provided, with one coupled to each device on the bus. Each pseudo busy circuit is controlled by a control signal from the initiator. The pseudo busy circuit intercepts the busy line of the SCSI bus and provides a pseudo busy signal to the busy line input of the device when instructed by the initiator; although this requires additional control lines in conjunction with the SCSI bus, it allows the use of standard peripherals connectors and controllers designed for the SCSI bus.
摘要翻译：本发明提供了一种用于动态地修改对总线的访问的优先级的方法和装置，其中总线具有分配在耦合到总线的设备中的控制和仲裁功能，每个设备具有固定的优先级。选择性地禁止由特定设备访问总线，防止它们断言其固定的优先级。在优选实施例中，本发明通过向SCSI设备提供伪忙信号来提供通过耦合到总线的多个SCSI设备来重新选择SCSI总线的控制，从而不需要重新选择。以这种方式，启动器可以向SCSI设备发出多个命令，并且在准备好时控制设备将被维护的顺序。提供了多个伪忙电路，其中一个耦合到总线上的每个设备。每个伪忙电路由来自启动器的控制信号控制。伪忙电路拦截SCSI总线的忙线，并在发起者指示的时候向设备的忙线输入提供伪忙信号; 尽管这需要与SCSI总线相结合的附加控制线，但它允许使用为SCSI总线设计的标准外设连接器和控制器。

3. 发明授权

US5274645A Disk array system 失效
标题翻译：磁盘阵列系统
公开(公告)号：US5274645A
公开(公告)日：1993-12-28
申请号：US872560
申请日：1992-04-23
申请人： Thomas E. Idleman , Robert S. Koontz , David T. Powers , David H. Jaffe , Larry P. Henson , Joseph S. Glider , Kumar Gajjar
发明人： Thomas E. Idleman , Robert S. Koontz , David T. Powers , David H. Jaffe , Larry P. Henson , Joseph S. Glider , Kumar Gajjar
IPC分类号： G06F3/06 , G06F11/00 , G06F11/10 , G06F11/20 , G11B20/18
CPC分类号： G06F11/10 , G06F11/1008 , G06F11/1076 , G06F11/1666 , G06F11/201 , G06F11/2089 , G06F11/2094 , G11B20/1833 , G06F11/0757 , G06F11/20
摘要： A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remains constant. The invention also includes switching circuitry which permits a functioning second level controller to assume control of a group of memory devices formerly primarily controlled by the failed second level controller. In addition, the invention provides error check and correction as well as mass storage device configuration circuitry.
摘要翻译：一种用于控制计算机和以特定逻辑配置排列的一组存储器件之间的数据流的方法和装置。该系统包括一组第一级控制器和一组二级控制器。第一级控制器和第二级控制器协同工作，使得如果第二级控制器之一发生故障，则将第一级控制器与存储设备之间的路由切换到正常运行的第二级控制器，而无需使计算机进入重新路由过程。存储器件的逻辑配置保持不变。本发明还包括切换电路，其允许正常工作的第二电平控制器控制先前由故障的第二电平控制器控制的一组存储器装置。此外，本发明提供错误检查和校正以及大容量存储设备配置电路。

4. 发明授权

US5212785A Apparatus and method for controlling data flow between a computer and memory devices 失效
标题翻译：用于控制计算机和存储器件之间的数据流的装置和方法
公开(公告)号：US5212785A
公开(公告)日：1993-05-18
申请号：US506703
申请日：1990-04-06
申请人： David T. Powers , David H. Jaffe , Larry P. Henson , Hoke S. Johnson III , Joseph S. Glider , Thomas E. Idleman
发明人： David T. Powers , David H. Jaffe , Larry P. Henson , Hoke S. Johnson III , Joseph S. Glider , Thomas E. Idleman
IPC分类号： G06F11/00 , G06F11/10 , G06F11/20 , G11B20/18
CPC分类号： G06F11/2092 , G06F11/1076 , G11B20/1833 , G06F11/0757 , G06F11/2033
摘要： A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remains constant. The invention also includes switching circuitry which permits a functioning second level controller to assume control of a group of memory devices formerly primarily controlled by the failed second level controller.
摘要翻译：一种用于控制计算机和以特定逻辑配置排列的一组存储器件之间的数据流的方法和装置。该系统包括一组第一级控制器和一组二级控制器。第一级控制器和第二级控制器协同工作，使得如果第二级控制器之一发生故障，则将第一级控制器与存储设备之间的路由切换到正常运行的第二级控制器，而无需使计算机进入重新路由过程。存储器件的逻辑配置保持不变。本发明还包括切换电路，其允许正常工作的第二电平控制器控制先前由故障的第二电平控制器控制的一组存储器装置。

5. 发明授权

US5140592A Disk array system 失效
标题翻译：磁盘阵列系统
公开(公告)号：US5140592A
公开(公告)日：1992-08-18
申请号：US601482
申请日：1990-10-22
申请人： Thomas E. Idleman , Robert S. Koontz , David T. Powers , David H. Jaffe , Larry P. Henson , Joseph S. Glider , Kumar Gajjar
发明人： Thomas E. Idleman , Robert S. Koontz , David T. Powers , David H. Jaffe , Larry P. Henson , Joseph S. Glider , Kumar Gajjar
IPC分类号： G06F3/06 , G06F11/00 , G06F11/10 , G06F11/20 , G11B20/18
CPC分类号： G06F11/10 , G06F11/1008 , G06F11/1076 , G06F11/1666 , G06F11/201 , G06F11/2089 , G06F11/2094 , G11B20/1833 , G06F11/0757 , G06F11/20
摘要： A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remain constant. The invention also includes switching circuitry which permits a functioning second level controller to assume control of a group of memory devices formerly primarily contolled by the failed second level controller. In addition, the invention provides error check and correction as well as mass storage device configuration circuitry.
摘要翻译：一种用于控制计算机和以特定逻辑配置排列的一组存储器件之间的数据流的方法和装置。该系统包括一组第一级控制器和一组二级控制器。第一级控制器和第二级控制器协同工作，使得如果第二级控制器之一发生故障，则将第一级控制器与存储设备之间的路由切换到正常运行的第二级控制器，而无需使计算机进入重新路由过程。存储器件的逻辑配置保持不变。本发明还包括切换电路，其允许正常工作的第二电平控制器控制先前主要由故障的第二电平控制器调制的一组存储设备。此外，本发明提供错误检查和校正以及大容量存储设备配置电路。

6. 发明授权

US5134619A Failure-tolerant mass storage system 失效
标题翻译：不耐受的大容量存储系统
公开(公告)号：US5134619A
公开(公告)日：1992-07-28
申请号：US505622
申请日：1990-04-06
申请人： Larry P. Henson , Kumar Gajjar , David T. Powers , Thomas E. Idleman
发明人： Larry P. Henson , Kumar Gajjar , David T. Powers , Thomas E. Idleman
IPC分类号： G06F11/00 , G06F11/10 , G06F11/20 , G11B20/18
CPC分类号： G06F11/10 , G06F11/1076 , G06F11/1666 , G06F11/201 , G06F11/2094 , G11B20/1833 , G06F11/0757 , G06F11/20 , G06F11/2089 , G06F2211/1057
摘要： A mass memory system for digital computers is disclosed. The system has a plurality of disk drives coupled to a plurality of small buffers. An Error Correction Controller is coupled to a plurality of X-bar switches, the X-bar switches being connected between each disk drive and its buffers. Data is read from and written to the disk drives in parallel and error correction is also performed in parallel. The X-bar switches are used to couple and decouple functional and nonfunctional disk drives to the system as necessary. Likewise, the buffers can be disconnected from the system should they fail. The parallel architecture, combined with a Reed-Solomon error detection and correction scheme and X-bar switches allows the system to tolerate and correct any two failed drives, allowing for high fault-tolerance operation.
摘要翻译：公开了一种用于数字计算机的大容量存储器系统。该系统具有耦合到多个小缓冲器的多个盘驱动器。错误校正控制器耦合到多个X-bar开关，X-bar开关连接在每个磁盘驱动器及其缓冲器之间。数据从并行写入磁盘驱动器并且并行执行错误纠正。 X-bar开关用于根据需要将功能和非功能磁盘驱动器耦合到系统。同样，缓冲区可以与系统断开连接。并行架构与Reed-Solomon错误检测和校正方案以及X-bar开关相结合，允许系统容忍和纠正任何两个故障的驱动器，从而实现高容错运行。

7. 发明授权

US5956524A System and method for dynamic alignment of associated portions of a code word from a plurality of asynchronous sources 失效
标题翻译：用于从多个异步源的代码字的关联部分的动态对齐的系统和方法
公开(公告)号：US5956524A
公开(公告)日：1999-09-21
申请号：US891213
申请日：1997-07-10
申请人： Kumar Gajjar , Larry P. Henson
发明人： Kumar Gajjar , Larry P. Henson
IPC分类号： G06F11/10 , G06F11/00
CPC分类号： G06F11/1008
摘要： The present invention is directed to a novel apparatus for "on-the-fly" data correction and regeneration of a plurality of data read from and stored to a plurality of storage devices. A control circuit is provided for control of data flow to and from the storage devices. The control circuit establishes and maintains a relatively simple semaphore between itself and an interface circuit controlling a FIFO buffer. A mask register is provided as a type of programmable logic AND gate to assert a master ready signal when each of a selected plurality of the interface circuits, one interface circuit per FIFO buffer, indicates that its respective FIFO buffer is ready, either to output or input an entire block. When each is ready, routing and correction commences under control of the control circuit until an entire block has been processed. Each interface circuit includes an associated flip/flop having an output which provides an indication of the ready status. When the flip/flop is set by the interface circuit, the FIFO buffer is ready. When the control circuit resets the flip/flop, the interface circuit establishes that an entire block has been processed.
摘要翻译：本发明涉及一种用于对从多个存储装置读取并存储的多个数据进行“即时”数据校正和再生的新装置。提供控制电路用于控制往返于存储设备的数据流。控制电路在其自身和控制FIFO缓冲器的接口电路之间建立并维持相对简单的信号量。当选择的多个接口电路（每个FIFO缓冲器的一个接口电路）中的每个接口电路指示其各自的FIFO缓冲器准备就绪时，提供屏蔽寄存器作为一种类型的可编程逻辑与门来断言主准备信号，以输出或输入整个块。当每个都准备就绪时，路由和校正在控制电路的控制下开始，直到整个块被处理。每个接口电路包括具有提供就绪状态指示的输出的相关联的触发器。当触发器由接口电路设置时，FIFO缓冲器就绪。当控制电路复位触发器时，接口电路确定整个块已被处理。

8. 发明授权

US06385674B1 Systems and methods for dynamic alignment of associated portions of a code word from a plurality of asynchronous sources 有权
标题翻译：用于从多个异步源的代码字的关联部分的动态对准的系统和方法
公开(公告)号：US06385674B1
公开(公告)日：2002-05-07
申请号：US09399581
申请日：1999-09-20
申请人： Kumar Gajjar , Larry P. Henson
发明人： Kumar Gajjar , Larry P. Henson
IPC分类号： G06F1100
CPC分类号： G06F11/1008
摘要： The present invention is directed to a novel apparatus for “on-the-fly” data correction and regeneration of a plurality of data read from and stored to a plurality of storage devices. A control circuit is provided for control of data flow to and from the storage devices. The control circuit establishes and maintains a relatively simple semaphore between itself and an interface circuit controlling a FIFO buffer. A mask register is provided as a type of programmable logic AND gate to assert a master ready signal when each of a selected plurality of the interface circuits, one interface circuit per FIFO buffer, indicates that its respective FIFO buffer is ready, either to output or input an entire block. When each is ready, routing and correction commences under control of the control circuit until an entire block has been processed. Each interface circuit includes an associated flip/flop having an output which provides an indication of the ready status. When the flip/flop is set by the interface circuit, the FIFO buffer is ready. When the control circuit resets the flip/flop, the interface circuit establishes that an entire block has been processed.
摘要翻译：本发明涉及一种用于对从多个存储装置读取并存储的多个数据进行“即时”数据校正和再生的新装置。提供控制电路用于控制往返于存储设备的数据流。控制电路在其自身和控制FIFO缓冲器的接口电路之间建立并维持相对简单的信号量。当选择的多个接口电路（每个FIFO缓冲器的一个接口电路）中的每个接口电路指示其各自的FIFO缓冲器准备就绪时，提供屏蔽寄存器作为一种类型的可编程逻辑与门来断言主准备信号，以输出或输入整个块。当每个都准备就绪时，路由和校正在控制电路的控制下开始，直到整个块被处理。每个接口电路包括具有提供就绪状态指示的输出的相关联的触发器。当触发器由接口电路设置时，FIFO缓冲器就绪。当控制电路复位触发器时，接口电路确定整个块已被处理。

9. 发明授权

US5715406A Controlled bus reselection interface and method 失效
标题翻译：控制总线重选接口和方法
公开(公告)号：US5715406A
公开(公告)日：1998-02-03
申请号：US336630
申请日：1994-11-09
申请人： Larry P. Henson , Kumar Gajjar , Thomas E. Idleman
发明人： Larry P. Henson , Kumar Gajjar , Thomas E. Idleman
IPC分类号： G06F13/36 , G06F13/374 , G06F13/42
CPC分类号： G06F13/374 , G06F13/36
摘要： The present invention provides a method and apparatus for dynamically modifying the priority of access to a bus, where the bus has control and arbitration functions distributed among the devices coupled to the bus, with each device having a fixed priority level. Access to the bus by particular devices is selectively inhibited, preventing them from asserting their fixed priority level. In a preferred embodiment, the present invention provides control over the reselection of a SCSI bus by a plurality of SCSI devices coupled to the bus by providing a pseudo busy signal to SCSI devices from which reselection is not desired. In this fashion, an initiator may issue a plurality of commands to the SCSI devices and control the order in which the devices will be serviced when ready. A plurality of pseudo busy circuits are provided, with one coupled to each device on the bus. Each pseudo busy circuit is controlled by a control signal from the initiator. The pseudo busy circuit intercepts the busy line of the SCSI bus and provides a pseudo busy signal to the busy line input of the device when instructed by the initiator, although this requires additional control lines in conjunction with the SCSI bus, it allows the use of standard peripherals connectors and controllers designed for the SCSI bus.
摘要翻译：本发明提供了一种用于动态地修改对总线的访问的优先级的方法和装置，其中总线具有分配在耦合到总线的设备中的控制和仲裁功能，每个设备具有固定的优先级。选择性地禁止由特定设备访问总线，防止它们断言其固定的优先级。在优选实施例中，本发明通过向SCSI设备提供伪忙信号来提供通过耦合到总线的多个SCSI设备来重新选择SCSI总线的控制，从而不需要重新选择。以这种方式，启动器可以向SCSI设备发出多个命令，并且在准备好时控制设备将被维护的顺序。提供了多个伪忙电路，其中一个耦合到总线上的每个设备。每个伪忙电路由来自启动器的控制信号控制。伪忙电路拦截SCSI总线的忙线，并且在发起者的指示下，向设备的忙线路输入提供伪忙信号，尽管这需要与SCSI总线相结合的附加控制线，但是它允许使用为SCSI总线设计的标准外设连接器和控制器。

10. 发明授权

US5285451A Failure-tolerant mass storage system 失效
标题翻译：容错大容量存储系统
公开(公告)号：US5285451A
公开(公告)日：1994-02-08
申请号：US914662
申请日：1992-07-15
申请人： Larry P. Henson , Kumar Gajjar , David T. Powers , Thomas E. Idleman
发明人： Larry P. Henson , Kumar Gajjar , David T. Powers , Thomas E. Idleman
IPC分类号： G06F11/00 , G06F11/10 , G06F11/20 , G11B20/18
CPC分类号： G06F11/10 , G06F11/1076 , G06F11/1666 , G06F11/201 , G06F11/2094 , G11B20/1833 , G06F11/0757 , G06F11/20 , G06F11/2089 , G06F2211/1057
摘要： A mass memory system for digital computers is disclosed. The system has a plurality of disk drives coupled to a plurality of small buffers. An Error Correction Controller is coupled to a plurality of X-bar switches, the X-bar switches being connected between each disk drive and its buffers. Data is read from and written to the disk drives in parallel and error correction is also performed in parallel. The X-bar switches are used to couple and decouple functional and nonfunctional disk drives to the system as necessary. Likewise, the buffers can be disconnected from the system should they fail. The parallel architecture, combined with a Reed-Solomon error detection and correction scheme and X-bar switches allows the system to tolerate and correct any two failed drives, allowing for high fault-tolerance operation.
摘要翻译：公开了一种用于数字计算机的大容量存储器系统。该系统具有耦合到多个小缓冲器的多个盘驱动器。错误校正控制器耦合到多个X-bar开关，X-bar开关连接在每个磁盘驱动器及其缓冲器之间。数据从并行写入磁盘驱动器并且并行执行错误纠正。 X-bar开关用于根据需要将功能和非功能磁盘驱动器耦合到系统。同样，缓冲区可以与系统断开连接。并行架构与Reed-Solomon错误检测和校正方案以及X-bar开关相结合，允许系统容忍和纠正任何两个故障的驱动器，从而实现高容错运行。

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