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    • 1. 发明授权
    • Auto regression tester for network-based storage virtualization system
    • 基于网络的存储虚拟化系统的自动回归测试仪
    • US08132058B1
    • 2012-03-06
    • US11397487
    • 2006-04-03
    • Kumar GajjarRobert RobbinsRanjit Ghate
    • Kumar GajjarRobert RobbinsRanjit Ghate
    • G06F11/00
    • G06F11/263
    • An apparatus and method for testing a network-based storage virtualization system. A tester is connected to a host side of a storage virtualization system. The tester provides test scripts to the storage virtualization system to test I/O and other operations. A separate link, independent of said storage virtualization system, is provided to a storage side of said storage virtualization system to allow verification of the correct translation from virtual to physical independent of the data path used by the virtualization system. Thus, the tester verifies, over the separate link, the physical configuration of VLUNs and data written to the VLUNs by the tester on storage devices.
    • 一种用于测试基于网络的存储虚拟化系统的设备和方法。 测试器连接到存储虚拟化系统的主机端。 测试人员向存储虚拟化系统提供测试脚本,以测试I / O和其他操作。 独立于所述存储虚拟化系统的单独链接被提供给所述存储虚拟化系统的存储侧,以允许验证与虚拟化系统使用的数据路径无关的从虚拟到物理的正确转换。 因此,测试者通过​​单独的链路验证VLUN的物理配置和测试仪在存储设备上写入VLUN的数据。
    • 5. 发明授权
    • Bridge for direct data storage device access
    • 用于直接访问数据存储设备的桥
    • US06253271B1
    • 2001-06-26
    • US09372707
    • 1999-08-11
    • Tamir RamJohn V. VincenetKumar GajjarSara AbrahamSyang Edward SyuPaul Lester Popelka
    • Tamir RamJohn V. VincenetKumar GajjarSara AbrahamSyang Edward SyuPaul Lester Popelka
    • G06F1516
    • G06F13/4004
    • A bridge in a file server provides a direct link to data storage devices in satisfaction of data requests. The file server has one or more function-specific processors, including network processors (NPs) and file storage processors (FSPs), all operating in parallel and communicating over an interconnect bus. Each FSP is also connected to one or more disk controllers which in turn manage one or more data storage devices. To minimize local bus contention between data storage devices and network communications, separate internal buses are provided in the FSP, one internal bus connected to the interconnect bus for network communications and one internal bus connected to disk controllers for performing I/O operations on data storage devices. The bridge provides a path between the FSP's internal buses so that, for disk access requests, data from a particular data storage device may be sent by the disk controller via the bridge over the interconnect bus to the NP servicing the request with minimal involvement of the local FSP processor.
    • 文件服务器中的一个桥接器可以直接链接到满足数据请求的数据存储设备。 文件服务器具有一个或多个功能特定的处理器,包括网络处理器(NP)和文件存储处理器(FSP),所有这些处理器都通过并行运行并通过互连总线进行通信。 每个FSP还连接到一个或多个磁盘控制器,磁盘控制器又管理一个或多个数据存储设备。 为了最小化数据存储设备和网络通信之间的局部总线争用,FSP中提供单独的内部总线,一条内部总线连接到互连总线进行网络通信,一条内部总线连接到磁盘控制器,用于对数据存储执行I / O操作 设备。 该桥提供了FSP内部总线之间的路径,因此,对于磁盘访问请求,来自特定数据存储设备的数据可以由磁盘控制器通过互连总线上的桥发送到NP,以最少的参与 本地FSP处理器。
    • 9. 发明授权
    • Systems and methods for dynamic alignment of associated portions of a code word from a plurality of asynchronous sources
    • 用于从多个异步源的代码字的关联部分的动态对准的系统和方法
    • US06385674B1
    • 2002-05-07
    • US09399581
    • 1999-09-20
    • Kumar GajjarLarry P. Henson
    • Kumar GajjarLarry P. Henson
    • G06F1100
    • G06F11/1008
    • The present invention is directed to a novel apparatus for “on-the-fly” data correction and regeneration of a plurality of data read from and stored to a plurality of storage devices. A control circuit is provided for control of data flow to and from the storage devices. The control circuit establishes and maintains a relatively simple semaphore between itself and an interface circuit controlling a FIFO buffer. A mask register is provided as a type of programmable logic AND gate to assert a master ready signal when each of a selected plurality of the interface circuits, one interface circuit per FIFO buffer, indicates that its respective FIFO buffer is ready, either to output or input an entire block. When each is ready, routing and correction commences under control of the control circuit until an entire block has been processed. Each interface circuit includes an associated flip/flop having an output which provides an indication of the ready status. When the flip/flop is set by the interface circuit, the FIFO buffer is ready. When the control circuit resets the flip/flop, the interface circuit establishes that an entire block has been processed.
    • 本发明涉及一种用于对从多个存储装置读取并存储的多个数据进行“即时”数据校正和再生的新装置。 提供控制电路用于控制往返于存储设备的数据流。 控制电路在其自身和控制FIFO缓冲器的接口电路之间建立并维持相对简单的信号量。 当选择的多个接口电路(每个FIFO缓冲器的一个接口电路)中的每个接口电路指示其各自的FIFO缓冲器准备就绪时,提供屏蔽寄存器作为一种类型的可编程逻辑与门来断言主准备信号,以输出或 输入整个块。 当每个都准备就绪时,路由和校正在控制电路的控制下开始,直到整个块被处理。 每个接口电路包括具有提供就绪状态指示的输出的相关联的触发器。 当触发器由接口电路设置时,FIFO缓冲器就绪。 当控制电路复位触发器时,接口电路确定整个块已被处理。
    • 10. 发明授权
    • Controlled bus reselection interface and method
    • 控制总线重选接口和方法
    • US5715406A
    • 1998-02-03
    • US336630
    • 1994-11-09
    • Larry P. HensonKumar GajjarThomas E. Idleman
    • Larry P. HensonKumar GajjarThomas E. Idleman
    • G06F13/36G06F13/374G06F13/42
    • G06F13/374G06F13/36
    • The present invention provides a method and apparatus for dynamically modifying the priority of access to a bus, where the bus has control and arbitration functions distributed among the devices coupled to the bus, with each device having a fixed priority level. Access to the bus by particular devices is selectively inhibited, preventing them from asserting their fixed priority level. In a preferred embodiment, the present invention provides control over the reselection of a SCSI bus by a plurality of SCSI devices coupled to the bus by providing a pseudo busy signal to SCSI devices from which reselection is not desired. In this fashion, an initiator may issue a plurality of commands to the SCSI devices and control the order in which the devices will be serviced when ready. A plurality of pseudo busy circuits are provided, with one coupled to each device on the bus. Each pseudo busy circuit is controlled by a control signal from the initiator. The pseudo busy circuit intercepts the busy line of the SCSI bus and provides a pseudo busy signal to the busy line input of the device when instructed by the initiator, although this requires additional control lines in conjunction with the SCSI bus, it allows the use of standard peripherals connectors and controllers designed for the SCSI bus.
    • 本发明提供了一种用于动态地修改对总线的访问的优先级的方法和装置,其中总线具有分配在耦合到总线的设备中的控制和仲裁功能,每个设备具有固定的优先级。 选择性地禁止由特定设备访问总线,防止它们断言其固定的优先级。 在优选实施例中,本发明通过向SCSI设备提供伪忙信号来提供通过耦合到总线的多个SCSI设备来重新选择SCSI总线的控制,从而不需要重新选择。 以这种方式,启动器可以向SCSI设备发出多个命令,并且在准备好时控制设备将被维护的顺序。 提供了多个伪忙电路,其中一个耦合到总线上的每个设备。 每个伪忙电路由来自启动器的控制信号控制。 伪忙电路拦截SCSI总线的忙线,并且在发起者的指示下,向设备的忙线路输入提供伪忙信号,尽管这需要与SCSI总线相结合的附加控制线,但是它允许使用 为SCSI总线设计的标准外设连接器和控制器。