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1. 发明申请

WO1996028850A1 SERIES CAPACITOR CHARGE PUMP 审中-公开
标题翻译：系列电容充电泵
公开(公告)号：WO1996028850A1
公开(公告)日：1996-09-19
申请号：PCT/US1995003069
申请日：1995-03-09
申请人： MACRONIX INTERNATIONAL CO., LTD. , NKK CORPORATION , KAMEI, Teruhiko , LEE, I-Long , SOEJIMA, Kouta , WAN, Ray-Lin
发明人： MACRONIX INTERNATIONAL CO., LTD. , NKK CORPORATION
IPC分类号： H01L29/78
CPC分类号： H01L27/0222 , H02M3/073
摘要： A charge pump apparatus comprises first and second active capacitors (100/101) in series, having a common node (103) between them. The second lead of the second active capacitor (101) is coupled to a particular node (OUT) which drives an output of the charge pump. A pump clock (CLK0) is connected to the first lead of the first active capacitor (100). A voltage clamp (105) is connected to the particular node (OUT) and provides a bias point. A dynamic biasing circuit (108) is connected to the common node (103) and charges the common node (103) and the particular node (OUT) between transitions of the pump clock (CLK0) to keep both active capacitors (100/101) activated during the transitions. The dynamic biasing circuit (108) includes a precharge circuit (63/64) responsive to a charge clock (CLKB) wherein the charge clock (CLKB) has transitions non-overlapping with transitions of the pump clock (CLK0).
摘要翻译：电荷泵装置包括串联的第一和第二有源电容器（100/101），它们之间具有公共节点（103）。第二有源电容器（101）的第二引线耦合到驱动电荷泵的输出的特定节点（OUT）。泵时钟（CLK0）连接到第一有源电容器（100）的第一引线。电压钳（105）连接到特定节点（OUT）并提供偏置点。动态偏置电路（108）连接到公共节点（103），并且在泵时钟（CLK0）的转换之间对公共节点（103）和特定节点（OUT）充电以保持有源电容器（100/101）在转换期间激活。动态偏置电路（108）包括响应于充电时钟（CLKB）的充电电路（63/64），其中充电时钟（CLKB）具有与泵浦时钟（CLK0）的转换不重叠的转变。

2. 发明申请

WO1998010424A1 FOWLER-NORDHEIM (F-N) TUNNELING FOR PRE-PROGRAMMING IN A FLOATING GATE MEMORY DEVICE 审中-公开
标题翻译： FOWLER-NORDHEIM（F-N）隧道在浮动门存储器件中的预编程
公开(公告)号：WO1998010424A1
公开(公告)日：1998-03-12
申请号：PCT/US1997003861
申请日：1997-03-10
申请人： MACRONIX INTERNATIONAL CO., LTD. , HUNG, Chun, Hsiung , SHIAU, Tzeng-Huei , CHENG, Yao-Wu , LEE, I.-Long , SHONE, Fuchia , WAN, Ray-Lin
发明人： MACRONIX INTERNATIONAL CO., LTD.
IPC分类号： G11C11/34
CPC分类号： G11C16/107 , G11C16/0416 , G11C16/16 , G11C16/3454 , G11C16/3459 , H01L27/115
摘要： A new flash memory cell structure comprising a floating gate memory cell is made in a semiconductor substrate (10) having a first conductivity type, such as p-type. A first well (11) within the substrate by having a second conductivity type different from the first conductivity is included. A second well (12) within the first well is also included having the first conductivity type. A drain (14) and a source (13) are formed in the second well having the second conductivity type, and spaced away from one another to define a channel area between the drain (14) and the source (13). A floating gate (15) and a control gate (17) structure is included over the channel area. The floating gate memory cell is coupled with circuits that induce F-N tunneling of electrons out of the floating gate (15) into the channel area of the substrate (10) for erasing by applying a positive voltage to the second well (12), such as a voltage higher than the supply voltage, applying a positive voltage to the first well (11), which is substantially equal to the positive voltage of the second well (12), applying a negative voltage to the control gate (17) of the cell, while the substrate (10) is grounded.
摘要翻译：包括浮动栅极存储单元的新的闪速存储单元结构在具有第一导电类型的半导体衬底（10）中制成，例如p型。包括具有不同于第一导电性的第二导电类型的衬底内的第一阱（11）。第一阱中的第二阱（12）也包括具有第一导电类型。在具有第二导电类型的第二阱中形成漏极（14）和源极（13），并且彼此间隔开以限定漏极（14）和源极（13）之间的沟道区域。在通道区域上包括浮动栅极（15）和控制栅极（17）结构。浮动栅极存储单元与电路耦合，电路通过向第二阱（12）施加正电压而将电子的FN隧穿从浮动栅极（15）引入到衬底（10）的沟道区域中以进行擦除，例如电压高于所述电源电压，向所述第一阱（11）施加正电压，所述正电压基本上等于所述第二阱（12）的正电压，向所述电池的控制栅极（17）施加负电压而衬底（10）接地。

3. 发明申请

WO1997019452A1 METHOD AND SYSTEM FOR SOFT PROGRAMMING ALGORITHM 审中-公开
标题翻译：软件编程算法的方法与系统
公开(公告)号：WO1997019452A1
公开(公告)日：1997-05-29
申请号：PCT/US1995015051
申请日：1995-11-17
申请人： MACRONIX INTERNATIONAL CO., LTD. , YIU, Tom, Dang-Hsing , SHONE, Fuchia , LEE, I-Long , CHEN, Chia-Shing , CHEN, Hun-Song , LIU, Yuan-Chang , SHIAU, Tzeng-Huei , CHANG, Kuen-Long , WAN, Ray-Lin
发明人： MACRONIX INTERNATIONAL CO., LTD.
IPC分类号： G11C07/00
CPC分类号： G11C16/3409 , G11C16/3404
摘要： A floating gate memory device which includes control circuits (2, 3, 4) to generate a repair pulse to repair over-erased cells so they may be repaired block-by-block (1). This invention includes repairing the cells by applying a repair pulse to the cell's bit line (10, 11) while maintaining the word line voltage above ground. In a different embodiment, the word line voltage is maintained at two different voltage levels above ground. In the first stage, the word line voltage is maintained between approximately 0.1 volts and 0.2 volts for approximately 100 ms while the repair pulse is applied. In the second stage, the word line voltage is maintained between approximately 0.4 volts and 0.5 volts for approximately 100 ms while the repair pulse is applied.
摘要翻译：一种浮动栅极存储器件，其包括控制电路（2,3,4），以产生修复脉冲以修复过擦除的单元，从而可以逐块修复（1）。本发明包括通过对单元的位线（10,11）施加修复脉冲，同时保持字线电压高于地面来修复单元。在不同的实施例中，字线电压保持在地面以上两个不同的电压电平。在第一阶段，当施加修复脉冲时，字线电压保持在大约0.1伏和0.2伏之间大约100毫秒。在第二阶段，当施加修复脉冲时，字线电压保持在大约0.4伏和0.5伏之间大约100毫秒。

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