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1. 发明申请

WO1997019452A1 METHOD AND SYSTEM FOR SOFT PROGRAMMING ALGORITHM 审中-公开
标题翻译：软件编程算法的方法与系统
公开(公告)号：WO1997019452A1
公开(公告)日：1997-05-29
申请号：PCT/US1995015051
申请日：1995-11-17
申请人： MACRONIX INTERNATIONAL CO., LTD. , YIU, Tom, Dang-Hsing , SHONE, Fuchia , LEE, I-Long , CHEN, Chia-Shing , CHEN, Hun-Song , LIU, Yuan-Chang , SHIAU, Tzeng-Huei , CHANG, Kuen-Long , WAN, Ray-Lin
发明人： MACRONIX INTERNATIONAL CO., LTD.
IPC分类号： G11C07/00
CPC分类号： G11C16/3409 , G11C16/3404
摘要： A floating gate memory device which includes control circuits (2, 3, 4) to generate a repair pulse to repair over-erased cells so they may be repaired block-by-block (1). This invention includes repairing the cells by applying a repair pulse to the cell's bit line (10, 11) while maintaining the word line voltage above ground. In a different embodiment, the word line voltage is maintained at two different voltage levels above ground. In the first stage, the word line voltage is maintained between approximately 0.1 volts and 0.2 volts for approximately 100 ms while the repair pulse is applied. In the second stage, the word line voltage is maintained between approximately 0.4 volts and 0.5 volts for approximately 100 ms while the repair pulse is applied.
摘要翻译：一种浮动栅极存储器件，其包括控制电路（2,3,4），以产生修复脉冲以修复过擦除的单元，从而可以逐块修复（1）。本发明包括通过对单元的位线（10,11）施加修复脉冲，同时保持字线电压高于地面来修复单元。在不同的实施例中，字线电压保持在地面以上两个不同的电压电平。在第一阶段，当施加修复脉冲时，字线电压保持在大约0.1伏和0.2伏之间大约100毫秒。在第二阶段，当施加修复脉冲时，字线电压保持在大约0.4伏和0.5伏之间大约100毫秒。

2. 发明申请

WO1996041346A1 AUTOMATIC PROGRAMMING ALGORITHM FOR PAGE MODE FLASH MEMORY WITH VARIABLE PROGRAMMING PULSE HEIGHT AND PULSE WIDTH 审中-公开
标题翻译：具有可变编程脉冲高度和脉冲宽度的页面模式闪存存储器的自动编程算法
公开(公告)号：WO1996041346A1
公开(公告)日：1996-12-19
申请号：PCT/US1995007376
申请日：1995-06-07
申请人： MACRONIX INTERNATIONAL CO., LTD. , NKK CORPORATION , CHEN, Chia, Shing , HUNG, Chun-Hsiung , KAMEI, Teruhiko , WAN, Ray-Lin
发明人： MACRONIX INTERNATIONAL CO., LTD. , NKK CORPORATION
IPC分类号： G11C11/34
CPC分类号： G11C16/10
摘要： A method for programming a flash memory array (10) which insures fast programming to substantially all of the cells in the array, without over-programming, based on providing a pattern of program retry pulses (62, 63, 64, 65, 66) which have respective pulse widths and pulse heights which vary according to a pattern. The pattern includes a combination of both increasing pulse widths and increasing pulse heights. The pattern includes a first phase which completes in a specified amount of time including a predetermined number of retries so that substantially all of the cells in the array are programmed within the first phase. A second phase of the pattern involves a sequence of higher energy pulses addressed to programming the slowest cells in the array. When used in a page program array, in which individual cells which are programmed fast do not receive subsequent retry pulses, a very fast and reliable programming scheme is achieved.
摘要翻译：一种用于对闪速存储器阵列（10）进行编程的方法，其基于提供程序重试脉冲（62,63,64,65,66）的模式，确保快速编程到阵列中的基本上所有的阵列中的单元，而不需要过度编程，其具有根据图案变化的各自的脉冲宽度和脉冲高度。该图案包括增加的脉冲宽度和增加的脉冲高度的组合。该模式包括第一阶段，其以指定的时间量完成，包括预定次数的重试，使得阵列中的基本上所有的单元在第一阶段内被编程。该模式的第二阶段涉及一系列更高能量的脉冲，寻址到对阵列中最慢的单元进行编程。当在页面程序阵列中使用时，其中被编程为快速的各个单元不接收后续重试脉冲，实现了非常快速和可靠的编程方案。

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