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1. 发明授权

US08551805B2 Methods of manufacturing phase-change memory devices 有权
标题翻译：制造相变存储器件的方法
公开(公告)号：US08551805B2
公开(公告)日：2013-10-08
申请号：US13469498
申请日：2012-05-11
申请人： Gyu-Hwan Oh , Doo-Hwan Park , Kyung-Min Chung
发明人： Gyu-Hwan Oh , Doo-Hwan Park , Kyung-Min Chung
IPC分类号： H01L21/00 , H01L21/44 , H01L21/4763 , H01L21/302 , H01L21/461 , H01L41/00
CPC分类号： H01L45/06 , H01L27/2409 , H01L29/861 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： A phase-change memory device includes a word line on a substrate and a phase-change memory cell on the word line and comprising a phase-change material pattern. The device also includes a non-uniform conductivity layer pattern comprising a conductive region on the phase-change material pattern and a non-conductive region contiguous therewith. The device further includes a bit line on the conductive region of the non-uniform conductivity layer pattern. In some embodiments, the phase-change memory cell may further include a diode on the word line, a heating electrode on the diode and wherein the phase-change material layer is disposed on the heating electrode. An ohmic contact layer and a contact plug may be disposed between the diode and the heating electrode.
摘要翻译：相变存储器件包括衬底上的字线和字线上的相变存储器单元，并且包括相变材料图案。该装置还包括不均匀的导电层图案，其包括相变材料图案上的导电区域和与其相邻的非导电区域。该器件还包括位于不均匀导电层图案的导电区上的位线。在一些实施例中，相变存储单元还可以包括字线上的二极管，二极管上的加热电极，并且其中相变材料层设置在加热电极上。欧姆接触层和接触插塞可以设置在二极管和加热电极之间。

2. 发明申请

US20120322223A1 METHODS OF MANUFACTURING PHASE-CHANGE MEMORY DEVICES 有权
标题翻译：制造相变存储器件的方法
公开(公告)号：US20120322223A1
公开(公告)日：2012-12-20
申请号：US13469498
申请日：2012-05-11
申请人： Gyu-Hwan Oh , Doo-Hwan Park , Kyung-Min Chung
发明人： Gyu-Hwan Oh , Doo-Hwan Park , Kyung-Min Chung
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , H01L27/2409 , H01L29/861 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： A phase-change memory device includes a word line on a substrate and a phase-change memory cell on the word line and comprising a phase-change material pattern. The device also includes a non-uniform conductivity layer pattern comprising a conductive region on the phase-change material pattern and a non-conductive region contiguous therewith. The device further includes a bit line on the conductive region of the non-uniform conductivity layer pattern. In some embodiments, the phase-change memory cell may further include a diode on the word line, a heating electrode on the diode and wherein the phase-change material layer is disposed on the heating electrode. An ohmic contact layer and a contact plug may be disposed between the diode and the heating electrode.
摘要翻译：相变存储器件包括衬底上的字线和字线上的相变存储器单元，并且包括相变材料图案。该装置还包括不均匀的导电层图案，其包括相变材料图案上的导电区域和与其相邻的非导电区域。该器件还包括位于不均匀导电层图案的导电区上的位线。在一些实施例中，相变存储单元还可以包括字线上的二极管，二极管上的加热电极，并且其中相变材料层设置在加热电极上。欧姆接触层和接触插塞可以设置在二极管和加热电极之间。

3. 发明申请

US20050067959A1 Plasma discharge method and plasma display using the same 失效
标题翻译：等离子放电法和等离子显示器使用相同
公开(公告)号：US20050067959A1
公开(公告)日：2005-03-31
申请号：US10942024
申请日：2004-09-16
申请人： Sang-Hun Jang , Hidekazu Hatanaka , Young-Mo Kim , Seong-Eui Lee , Xiaoqing Zeng , Kyung-Min Chung , Seung-Hyun Son , Gi-Young Kim , Hyoung-Bin Park
发明人： Sang-Hun Jang , Hidekazu Hatanaka , Young-Mo Kim , Seong-Eui Lee , Xiaoqing Zeng , Kyung-Min Chung , Seung-Hyun Son , Gi-Young Kim , Hyoung-Bin Park
IPC分类号： G09G3/20 , G09G3/288 , G09G3/291 , G09G3/293 , G09G3/294 , G09G3/297 , G09G3/298 , H01J11/12 , H01J11/14 , H01J11/22 , H01J11/24 , H01J11/26 , H01J11/28 , H01J11/32 , H01J11/34 , H01J17/16 , H01J17/49
CPC分类号： H01J11/12 , H01J11/24 , H01J11/38 , H01J2211/245 , H01J2217/49221
摘要： A plasma discharge method and a plasma display using the same. In the method, a sustain discharge uses a facing surfaces discharge and a surface discharge after an address discharge. The discharges occur in separate discharge areas, and priming particles generated by the discharges are exchanged. Thus, the stability and the efficiency of the sustain discharge increase, and a gap for the address discharge decreases to lower a breakdown voltage.
摘要翻译：等离子体放电方法和使用其的等离子体显示器。在该方法中，维持放电在寻址放电之后使用面对面放电和表面放电。放电发生在单独的放电区域，并且由放电产生的引发颗粒被交换。因此，维持放电的稳定性和效率增加，并且寻址放电的间隙减小以降低击穿电压。

4. 发明授权

US08703573B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08703573B2
公开(公告)日：2014-04-22
申请号：US13422487
申请日：2012-03-16
申请人： Gyu-Hwan Oh , Dong-Hyun Kim , Kyung-Min Chung , Dong-Hyun Im
发明人： Gyu-Hwan Oh , Dong-Hyun Kim , Kyung-Min Chung , Dong-Hyun Im
IPC分类号： H01L21/20
CPC分类号： H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/16 , H01L45/1683
摘要： A method of manufacturing the semiconductor device includes sequentially forming first to third mold layer patterns on a substrate and spaced apart from each other, forming a first semiconductor pattern between the first mold layer pattern and the second mold layer pattern, and a second semiconductor pattern between the second mold layer pattern and the third mold layer pattern, forming a first trench between the first mold layer pattern and the third mold layer pattern by removing a portion of the second mold layer pattern and portions of the first and second semiconductor patterns, depositing a material for a lower electrode conformally along side and bottom surfaces of the first trench, and forming first and second lower electrodes separated from each other on the first and second semiconductor patterns, respectively, by removing a portion of the material for a lower electrode positioned on the second mold layer pattern.
摘要翻译：制造半导体器件的方法包括在基片上依次形成第一至第三模层图案并彼此分开，在第一模层图案和第二模层图案之间形成第一半导体图案，以及第二半导体图案，第二模层图案和第三模层图案，通过去除第二模层图案的一部分和第一和第二半导体图案的部分，在第一模层图案和第三模层图案之间形成第一沟槽，用于下电极的材料沿着第一沟槽的侧表面和底表面共形地形成，并且通过移除位于第一和第二半导体图案上的下电极的材料的一部分，分别形成在第一和第二半导体图案上彼此分离的第一和第二下电极第二模层图案。

5. 发明申请

US20050057160A1 Plasma lamp 审中-公开
标题翻译：等离子灯
公开(公告)号：US20050057160A1
公开(公告)日：2005-03-17
申请号：US10902843
申请日：2004-08-02
申请人： Gi-young Kim , Deuk-seok Chung , Won-seok Kim , Young-mo Kim , Kyung-min Chung , Seung-hyun Son , Hyoung-bin Park
发明人： Gi-young Kim , Deuk-seok Chung , Won-seok Kim , Young-mo Kim , Kyung-min Chung , Seung-hyun Son , Hyoung-bin Park
IPC分类号： H01J61/62 , H01J1/304 , H01J61/30 , H01J61/54 , H01K1/62
CPC分类号： H01J61/542 , B82Y10/00 , H01J1/304 , H01J61/305 , H01J2201/30469
摘要： A plasma lamp includes a container filled with a discharge gas, a main discharge electrode unit located in the container and including a first electrode and a second electrode, which define a main discharge region of a first gap and generate a main discharge, and a preliminary discharge electrode unit having a high resistance unit and arranged on at least one of the first electrode and the second electrode, and located adjacent to the main discharge region to define a preliminary discharge region of a second gap, which is smaller than the first gap. The preliminary discharge electrode unit of the provided plasma lamp induces a preliminary discharge for a short time at a low voltage. A main discharge occurs conveniently due to charged particles generated by the preliminary discharge.
摘要翻译：等离子体灯包括填充有放电气体的容器，位于容器中的主放电电极单元，其包括限定第一间隙的主放电区域并产生主放电的第一电极和第二电极，以及初步放电电极单元，其具有高电阻单元，并且布置在第一电极和第二电极中的至少一个上，并且位于与主放电区域相邻的位置，以限定比第一间隙小的第二间隙的预放电区域。所提供的等离子体灯的预放电电极单元在低电压下短时间引起初步放电。由于由初始放电产生的带电粒子，可以方便地进行主放电。

6. 发明申请

US20160307842A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160307842A1
公开(公告)日：2016-10-20
申请号：US15006265
申请日：2016-01-26
申请人： Jong-Min BAEK , Sang-Hoon AHN , Woo-Kyung YOU , Byung-Hee KIM , Young-Ju PARK , Nae-in LEE , Kyung-Min CHUNG
发明人： Jong-Min BAEK , Sang-Hoon AHN , Woo-Kyung YOU , Byung-Hee KIM , Young-Ju PARK , Nae-in LEE , Kyung-Min CHUNG
IPC分类号： H01L23/522 , H01L27/088 , H01L23/535 , H01L23/532
CPC分类号： H01L27/0886 , H01L21/823431 , H01L21/823475
摘要： A semiconductor device includes a plurality of wiring structures spaced apart from each other, and an insulating interlayer structure. Each of the wiring structures includes a metal pattern and a barrier pattern covering a sidewall, a bottom surface, and an edge portion of a top surface of the metal pattern and not covering a central portion of the top surface of the metal pattern. The insulating interlayer structure contains the wiring structures therein, and has an air gap between the wiring structures.
摘要翻译：半导体器件包括彼此间隔开的多个布线结构和绝缘夹层结构。每个布线结构包括金属图案和覆盖金属图案的顶表面的侧壁，底表面和边缘部分并且不覆盖金属图案的顶表面的中心部分的阻挡图案。绝缘层间结构包含其中的布线结构，并且在布线结构之间具有气隙。

7. 发明授权

US08872148B2 Phase-change memory devices 有权
标题翻译：相变存储器件
公开(公告)号：US08872148B2
公开(公告)日：2014-10-28
申请号：US13735180
申请日：2013-01-07
申请人： Doo-Hwan Park , Gyu-Hwan Oh , Jeong-Min Park , Kyung-Min Chung
发明人： Doo-Hwan Park , Gyu-Hwan Oh , Jeong-Min Park , Kyung-Min Chung
IPC分类号： H01L27/10 , H01L45/00 , H01L27/24
CPC分类号： H01L45/06 , H01L27/2409 , H01L27/2463 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A phase-change memory device includes a diode, a plug, a doping layer pattern, a phase-change layer pattern and an upper electrode. The diode is disposed on a substrate. The plug is disposed on the diode and has a bottom surface whose area is equal to the area of a top surface of the diode. The plug is formed of metal or a conductive metallic compound. The doping layer pattern is disposed on the plug and has a bottom surface whose area is equal to the area of a top surface of the plug, and includes the same metal or conductive metallic compound as the plug. The phase-change layer pattern is disposed on the doping layer pattern. The upper electrode is disposed on the phase-change layer pattern.
摘要翻译：相变存储器件包括二极管，插头，掺杂层图案，相变层图案和上电极。二极管设置在基板上。插头设置在二极管上，并具有面积等于二极管顶表面面积的底面。插头由金属或导电金属化合物形成。掺杂层图案设置在插塞上，并且具有面积等于插头顶面的面积的底面，并且包括与插头相同的金属或导电金属化合物。相变层图案设置在掺杂层图案上。上电极配置在相变层图案上。

8. 发明申请

US20120282751A1 METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING FINE PATTERNS 审中-公开
标题翻译：制作精细图案的半导体器件的方法
公开(公告)号：US20120282751A1
公开(公告)日：2012-11-08
申请号：US13463342
申请日：2012-05-03
申请人： Gyu-hwan OH , Doo-hwan Park , Dong-hyun Im , Kyung-min Chung
发明人： Gyu-hwan OH , Doo-hwan Park , Dong-hyun Im , Kyung-min Chung
IPC分类号： H01L21/311 , H01L21/02 , H01L21/768 , H01L21/20
CPC分类号： H01L28/90 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76816 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/16 , H01L45/1683
摘要： A method of fabricating an integrated circuit device includes forming first and second patterns extending in first and second directions, respectively, on a target layer. The first patterns comprise a metal oxide and/or metal silicate material having an etch selectivity with respect to that of the target layer. The second patterns comprise a material having an etch selectivity with respect to those of the first patterns and the target layer. The target layer is selectively etched using the first patterns and the second patterns as an etch mask to define holes respectively extending through the target layer to expose a layer therebelow. At least one of the first and second patterns is formed using respective mask patterns formed by a photolithographic process, and the at least one of the first and second patterns have a finer pitch than that of the respective mask patterns.
摘要翻译：一种制造集成电路器件的方法包括分别在目标层上形成在第一和第二方向上延伸的第一和第二图案。第一图案包括具有相对于目标层的蚀刻选择性的金属氧化物和/或金属硅酸盐材料。第二图案包括相对于第一图案和目标层具有蚀刻选择性的材料。使用第一图案和第二图案作为蚀刻掩模来选择性地蚀刻目标层，以限定分别延伸穿过目标层的孔以暴露其下面的层。使用通过光刻工艺形成的各个掩模图案形成第一和第二图案中的至少一个，并且第一和第二图案中的至少一个具有比各个掩模图案更细的间距。

9. 发明申请

US20120252187A1 Semiconductor Device and Method of Manufacturing the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120252187A1
公开(公告)日：2012-10-04
申请号：US13422487
申请日：2012-03-16
申请人： Gyu-Hwan Oh , Dong-Hyun Kim , Kyung-Min Chung , Dong-Hyun Im
发明人： Gyu-Hwan Oh , Dong-Hyun Kim , Kyung-Min Chung , Dong-Hyun Im
IPC分类号： H01L21/329 , H01L21/283 , H01L21/02
CPC分类号： H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/16 , H01L45/1683
摘要： A method of manufacturing the semiconductor device includes sequentially forming first to third mold layer patterns on a substrate and spaced apart from each other , forming a first semiconductor pattern between the first mold layer pattern and the second mold layer pattern, and a second semiconductor pattern between the second mold layer pattern and the third mold layer pattern, forming a first trench between the first mold layer pattern and the third mold layer pattern by removing a portion of the second mold layer pattern and portions of the first and second semiconductor patterns, depositing a material for a lower electrode conformally along side and bottom surfaces of the first trench, and forming first and second lower electrodes separated from each other on the first and second semiconductor patterns, respectively, by removing a portion of the material for a lower electrode positioned on the second mold layer pattern.
摘要翻译：制造半导体器件的方法包括在基片上依次形成第一至第三模层图案并彼此分开，在第一模层图案和第二模层图案之间形成第一半导体图案，以及第二半导体图案，第二模层图案和第三模层图案，通过去除第二模层图案的一部分和第一和第二半导体图案的部分，在第一模层图案和第三模层图案之间形成第一沟槽，用于下电极的材料沿着第一沟槽的侧表面和底表面共形地形成，并且通过移除位于第一和第二半导体图案上的下电极的材料的一部分，分别形成在第一和第二半导体图案上彼此分离的第一和第二下电极第二模层图案。

10. 发明申请

US20120149166A1 METHOD OF FORMING TITANIUM NITRADE (TiN) FILM, NONVOLATILE MEMORY DEVICE USING THE TiN FILM, AND METHOD OF MANUFACTURING THE NONVOLATILE MEMORY DEVICE 审中-公开
标题翻译：使用TiN膜形成钛铁（TiN）膜，非易失存储器件的方法和制造非易失性存储器件的方法
公开(公告)号：US20120149166A1
公开(公告)日：2012-06-14
申请号：US13301047
申请日：2011-11-21
申请人： Young-Lim PARK , Jin-Il Lee , Kyung-Min Chung , Sug-Woo Jung , Chang-Su Kim
发明人： Young-Lim PARK , Jin-Il Lee , Kyung-Min Chung , Sug-Woo Jung , Chang-Su Kim
IPC分类号： H01L21/20 , H01L21/768
CPC分类号： C23C16/34 , C23C16/45529 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/16
摘要： A method of manufacturing a nonvolatile memory device includes forming an insulating film pattern, which includes apertures, on a substrate, forming a switching element in each of the apertures, forming a bottom electrode on the switching element by using a silicon (Si)-doped titanium nitride (TiN) film, and forming a variable resistance material pattern on the bottom electrode. The Si-doped TiN film is formed by repeatedly forming a TiN film and doping the TiN film with Si.
摘要翻译：一种制造非易失性存储器件的方法包括：在衬底上形成包括孔的绝缘膜图案，在每个孔中形成开关元件，通过使用硅（Si）掺杂在开关元件上形成底电极氮化钛（TiN）膜，并且在底部电极上形成可变电阻材料图案。通过重复形成TiN膜并用Si掺杂TiN膜来形成Si掺杂的TiN膜。

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