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1. 发明授权

US08609014B2 Template manufacturing method, semiconductor device manufacturing method and template 有权
标题翻译：模板制造方法，半导体器件制造方法和模板
公开(公告)号：US08609014B2
公开(公告)日：2013-12-17
申请号：US13150961
申请日：2011-06-01
申请人： Tsukasa Azuma , Tatsuhiko Higashiki , Kyoichi Suguro
发明人： Tsukasa Azuma , Tatsuhiko Higashiki , Kyoichi Suguro
IPC分类号： B29C67/20
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00
摘要： According to one embodiment, a template manufacturing method is a method for manufacturing a template for use in an imprint processing in which a pattern having irregularities are formed on a principal surface, and the pattern is brought into contact with a resist member formed on a substrate to be processed, to transfer the pattern to the resist member, the method including implanting charged particles at least into the bottoms of concave portions of the template.
摘要翻译：根据一个实施例，模板制造方法是用于制造在压印处理中使用的模板的方法，其中在主表面上形成具有凹凸的图案，并且图案与形成在基板上的抗蚀剂部件接触要被处理以将图案转印到抗蚀剂构件上，该方法包括将带电粒子至少注入到模板的凹部的底部中。

2. 发明授权

US08436331B2 Memory device and method for manufacturing same 失效
标题翻译：存储器件及其制造方法
公开(公告)号：US08436331B2
公开(公告)日：2013-05-07
申请号：US12844374
申请日：2010-07-27
申请人： Yoko Iwakaji , Jun Hirota , Kyoichi Suguro , Moto Yabuki
发明人： Yoko Iwakaji , Jun Hirota , Kyoichi Suguro , Moto Yabuki
IPC分类号： H01L21/02
CPC分类号： H01L27/1021 , G11C13/0007 , G11C2213/71 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/16 , H01L45/1675
摘要： According to one embodiment, a method for manufacturing a memory device is disclosed. The method includes forming a silicon diode. At least an upper portion of the silicon diode is made of a semiconductor material containing silicon and doped with impurity. The method includes forming a metal layer made of a metal on the silicon diode. The method includes forming a metal nitride layer made of a nitride of the metal on the metal layer. The method includes forming a resistance change film. In addition, the method includes reacting the metal layer with the silicon diode and the metal nitride layer by heat treatment to form an electrode film containing the metal, silicon, and nitrogen.
摘要翻译：根据一个实施例，公开了一种用于制造存储器件的方法。该方法包括形成硅二极管。至少硅二极管的上部由含有硅并掺杂杂质的半导体材料制成。该方法包括在硅二极管上形成由金属制成的金属层。该方法包括在金属层上形成由金属的氮化物制成的金属氮化物层。该方法包括形成电阻变化膜。此外，该方法包括通过热处理使金属层与硅二极管和金属氮化物层反应，以形成含有金属，硅和氮的电极膜。

3. 发明申请

US20110248361A1 SEMICONDUCTOR DEVICE WITH EXTENSION STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有延伸结构的半导体器件及其制造方法
公开(公告)号：US20110248361A1
公开(公告)日：2011-10-13
申请号：US13168183
申请日：2011-06-24
申请人： Takayuki ITO , Kyoichi SUGURO , Kouji MATSUO
发明人： Takayuki ITO , Kyoichi SUGURO , Kouji MATSUO
IPC分类号： H01L29/772
CPC分类号： H01L21/823857 , H01L21/823814 , H01L21/823842
摘要： A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in a surface portion of the semiconductor region. The first gate insulation film is formed on the semiconductor region between the source extension region and the drain extension region. The first gate insulation film is formed of a silicon oxide film or a silicon oxynitride film having a nitrogen concentration of 15 atomic % or less. The second gate insulation film is formed on the first gate insulation film and contains nitrogen at a concentration of between 20 atomic % and 57 atomic %. The gate electrode is formed on the second gate insulation film.
摘要翻译：半导体器件包括半导体区域，源极区域，漏极区域，源极延伸区域，漏极延伸区域，第一栅极绝缘膜，第二栅极绝缘膜和栅极电极。源极区域，漏极区域，源极延伸区域和漏极延伸区域形成在半导体区域的表面部分中。第一栅极绝缘膜形成在源极延伸区域和漏极延伸区域之间的半导体区域上。第一栅极绝缘膜由氮浓度为15原子％以下的氧化硅膜或氮氧化硅膜形成。第二栅极绝缘膜形成在第一栅极绝缘膜上，并且含有浓度为20原子％至57原子％之间的氮。栅电极形成在第二栅绝缘膜上。

4. 发明授权

US08017466B2 Semiconductor device and manufacturing method for the same 失效
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US08017466B2
公开(公告)日：2011-09-13
申请号：US12591162
申请日：2009-11-10
申请人： Kazuaki Nakajima , Kyoichi Suguro
发明人： Kazuaki Nakajima , Kyoichi Suguro
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28079 , H01L29/4958 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , Y10S438/976
摘要： In a semiconductor substrate on which are formed an N-type MOS transistor and a P-type MOS transistor, the gate electrode of the N-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the gate electrode of the P-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the concentration of carbon contained in the former tungsten film is less than the concentration of carbon contained in the latter tungsten film.
摘要翻译：在形成N型MOS晶体管和P型MOS晶体管的半导体衬底中，N型MOS晶体管的栅电极包括与栅极绝缘膜接触的钨膜和栅电极的P型MOS晶体管包括与栅极绝缘膜接触的钨膜，前者钨膜中所含的碳的浓度小于后者钨膜中所含的碳的浓度。

5. 发明申请

US20100062596A1 Semiconductor device and manufacturing method for the same 失效
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20100062596A1
公开(公告)日：2010-03-11
申请号：US12591162
申请日：2009-11-10
申请人： Kazuaki Nakajima , Kyoichi Suguro
发明人： Kazuaki Nakajima , Kyoichi Suguro
IPC分类号： H01L21/28
CPC分类号： H01L21/823842 , H01L21/28079 , H01L29/4958 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , Y10S438/976
摘要： In a semiconductor substrate on which are formed an N-type MOS transistor and a P-type MOS transistor, the gate electrode of the N-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the gate electrode of the P-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the concentration of carbon contained in the former tungsten film is less than the concentration of carbon contained in the latter tungsten film.
摘要翻译：在形成N型MOS晶体管和P型MOS晶体管的半导体衬底中，N型MOS晶体管的栅电极包括与栅极绝缘膜接触的钨膜和栅电极的P型MOS晶体管包括与栅极绝缘膜接触的钨膜，前者钨膜中所含的碳的浓度小于后者钨膜中所含的碳的浓度。

6. 发明授权

US07667274B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07667274B2
公开(公告)日：2010-02-23
申请号：US12071887
申请日：2008-02-27
申请人： Kazuaki Nakajima , Kyoichi Suguro
发明人： Kazuaki Nakajima , Kyoichi Suguro
IPC分类号： H01L29/45 , H01L29/78
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/76855 , H01L21/823814 , H01L21/823871 , H01L27/092
摘要： A semiconductor device is disclosed, which comprises a silicon substrate, a complementary MISFET circuit, an insulation film formed on the silicon substrate, a first contact hole formed in the insulation film, a first metal silicide layer formed on the bottom of the first contact hole, the first metal silicide layer being provided by a reaction of the n-channel impurity diffused region of the n-channel MISFET with a first metal, a second contact hole formed in the insulation film, a second metal silicide layer formed on the bottom of the second contact hole, the second metal silicide layer being provided by a reaction of the p-channel impurity diffused region of the p-channel MISFET with a second metal, and a work function of the second metal silicide layer being higher than that of the first metal silicide layer.
摘要翻译：公开了一种半导体器件，其包括硅衬底，互补MISFET电路，形成在硅衬底上的绝缘膜，形成在绝缘膜中的第一接触孔，形成在第一接触孔的底部上的第一金属硅化物层通过n沟道MISFET的n沟道杂质扩散区域与第一金属的反应提供第一金属硅化物层，形成在绝缘膜中的第二接触孔，形成在第二金属硅化物层的底部的第二金属硅化物层所述第二接触孔，所述第二金属硅化物层由所述p沟道MISFET的p沟道杂质扩散区域与第二金属的反应提供，并且所述第二金属硅化物层的功函数高于所述第二金属硅化物层的功函数第一金属硅化物层。

7. 发明申请

US20090203181A1 Semiconductor device manufacturing method, wiring and semiconductor device 有权
标题翻译：半导体器件制造方法，布线和半导体器件
公开(公告)号：US20090203181A1
公开(公告)日：2009-08-13
申请号：US12320655
申请日：2009-01-30
申请人： Kyoichi Suguro , Mitsuaki Izuha
发明人： Kyoichi Suguro , Mitsuaki Izuha
IPC分类号： H01L21/336
CPC分类号： H01L21/28052 , H01L21/823835 , H01L21/823842 , H01L21/823871 , H01L2924/0002 , H01L2924/00
摘要： In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a metallic material is thereafter formed on the regions and is heat-treated, thereby forming a silicide film on the semiconductor layer. In another embodiment, an impurity is introduced into the impurity segregation layer, and a film of a metallic material is thereafter formed on the impurity segregation layer and is heat-treated to form a silicide film.
摘要翻译：在本发明的实施例中，通过热处理形成具有分别引入p型杂质，n型杂质和（p + n）杂质的区域的半导体层作为表面层。除去这些区域上的杂质偏析层，然后在该区域上形成金属材料膜，并进行热处理，从而在半导体层上形成硅化物膜。在另一个实施方案中，将杂质引入杂质偏析层中，然后在杂质偏析层上形成金属材料膜，并进行热处理以形成硅化物膜。

8. 发明申请

US20080293225A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20080293225A1
公开(公告)日：2008-11-27
申请号：US12125497
申请日：2008-05-22
申请人： Kyoichi SUGURO
发明人： Kyoichi SUGURO
IPC分类号： H01L21/26
CPC分类号： H01L21/266 , H01L21/823878 , H01L21/823892
摘要： A method for manufacturing a semiconductor device including a first conductive type impurity region formed by introducing a first conductive type impurities in a first region of a semiconductor region and heating the first region, a second conductive type impurity region formed by introducing a second conductive type impurities in a second region of the semiconductor region and heating the second region, the method including covering the second region with a mask and then introducing the first conductive type impurities in a surface of the first region, removing the mask by a process using gas including oxygen while forming an oxide film on the surface of the first region by the processing using the gas including the oxygen, and introducing the second conductive type impurities in a surface of the second region by using the oxide film as a mask.
摘要翻译：一种制造半导体器件的方法，该半导体器件包括通过在半导体区域的第一区域中引入第一导电类型杂质并加热第一区域而形成的第一导电型杂质区，通过将第二导电类型杂质引入而形成的第二导电型杂质区所述半导体区域的第二区域并加热所述第二区域，所述方法包括用掩模覆盖所述第二区域，然后将所述第一导电类型杂质引入所述第一区域的表面中，通过使用包含氧的气体的工艺除去所述掩模，同时通过使用包含氧的气体的处理在第一区域的表面上形成氧化膜，并且通过使用氧化膜作为掩模将第二导电型杂质引入第二区域的表面。

9. 发明授权

US07354819B2 Method of manufacturing CMOS with silicide contacts 失效
标题翻译：用硅化物触点制造CMOS的方法
公开(公告)号：US07354819B2
公开(公告)日：2008-04-08
申请号：US10701435
申请日：2003-11-06
申请人： Kazuaki Nakajima , Kyoichi Suguro
发明人： Kazuaki Nakajima , Kyoichi Suguro
IPC分类号： H01L21/8238
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/76855 , H01L21/823814 , H01L21/823871 , H01L27/092
摘要： A semiconductor device is disclosed, which comprises a silicon substrate, a complementary MISFET circuit, an insulation film formed on the silicon substrate, a first contact hole formed in the insulation film, a first metal silicide layer formed on the bottom of the first contact hole, the first metal silicide layer being provided by a reaction of the n-channel impurity diffused region of the n-channel MISFET with a first metal, a second contact hole formed in the insulation film, a second metal silicide layer formed on the bottom of the second contact hole, the second metal silicide layer being provided by a reaction of the p-channel impurity diffused region of the p-channel MISFET with a second metal, and a work function of the second metal silicide layer being higher than that of the first metal silicide layer.
摘要翻译：公开了一种半导体器件，其包括硅衬底，互补MISFET电路，形成在硅衬底上的绝缘膜，形成在绝缘膜中的第一接触孔，形成在第一接触孔的底部上的第一金属硅化物层通过n沟道MISFET的n沟道杂质扩散区域与第一金属的反应提供第一金属硅化物层，形成在绝缘膜中的第二接触孔，形成在第二金属硅化物层的底部的第二金属硅化物层所述第二接触孔，所述第二金属硅化物层由所述p沟道MISFET的p沟道杂质扩散区域与第二金属的反应提供，并且所述第二金属硅化物层的功函数高于所述第二金属硅化物层的功函数第一金属硅化物层。

10. 发明授权

US07349750B2 Method for optimizing an industrial product, system for optimizing an industrial product and method for manufacturing an industrial product 失效
公开(公告)号：US07349750B2
公开(公告)日：2008-03-25
申请号：US11480373
申请日：2006-07-05
申请人： Kazumi Nishinohara , Mitsutoshi Nakamura , Kyoichi Suguro , Koji Shirai , Ichiro Taguchi
发明人： Kazumi Nishinohara , Mitsutoshi Nakamura , Kyoichi Suguro , Koji Shirai , Ichiro Taguchi
IPC分类号： G06F19/00
CPC分类号： G05B19/41885 , G05B2219/45031 , Y02P90/20 , Y02P90/26
摘要： A method for optimizing a structure of an industrial product includes selecting control factors from among manufacturing parameters affecting a target characteristic, which is scheduled to be manufactured by a sequence of manufacturing processes; setting levels to the respective control factors; selecting a reference characteristic having a trade-off relation with the target characteristic from among characteristics of the structure; setting a reference value to the reference characteristic; selecting a prior adjustment factor affecting the reference characteristic; creating conditions for experiments assigning combinations of the levels to the respective control factors; determining an adjustment value of the prior adjustment factor so that each of characteristic values of the reference characteristic obtained by the experiments conforms substantially to the reference value; and determining experimental characteristic values of the target characteristic using the adjustment value.

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