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1. 发明申请

WO2013081587A1 INSTRUCTION AND LOGIC TO PROVIDE VECTOR HORIZONTAL MAJORITY VOTING FUNCTIONALITY 审中-公开
标题翻译：指令和逻辑提供向量水平主要投票功能
公开(公告)号：WO2013081587A1
公开(公告)日：2013-06-06
申请号：PCT/US2011/062487
申请日：2011-11-30
申请人： INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , KSHITIJ, Doshi A. , SAIR, Suleyman , YOUNT, Charles R.
发明人： OULD-AHMED-VALL, Elmoustapha , KSHITIJ, Doshi A. , SAIR, Suleyman , YOUNT, Charles R.
IPC分类号： G06F9/30 , G06F9/305 , G06F9/06
CPC分类号： G06F9/30036 , G06F7/22 , G06F7/544 , G06F9/30018 , G06F9/30021 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F11/1048 , G06F11/1479
摘要： Instructions and logic provide vector horizontal majority voting functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read a number of values from data fields of the specified size in the source operand, corresponding to the mask specified by the instruction and store a result value to that number of corresponding data fields in the destination operand, the result value computed from the majority of values read from the number of data fields of the source operand.
摘要翻译：指令和逻辑提供向量横向多数投票功能。一些实施例，响应于指定目的地操作数，向量元素的大小，源操作数和对应于源操作数中的向量元素数据字段的一部分的掩码的指令; 从源操作数中的指定大小的数据字段读取一些数值，对应于指令指定的掩码，并将结果值存储到目标操作数中的相应数据字段数，从大多数从源操作数的数据字段数读取的值。

2. 发明申请

WO2013081588A1 INSTRUCTION AND LOGIC TO PROVIDE VECTOR HORIZONTAL COMPARE FUNCTIONALITY 审中-公开
标题翻译：指令和逻辑提供矢量水平比较功能
公开(公告)号：WO2013081588A1
公开(公告)日：2013-06-06
申请号：PCT/US2011/062488
申请日：2011-11-30
申请人： INTEL CORPORATION , OULD-AHMED-VALL, Elmoustapha , YOUNT, Charles R. , SAIR, Suleyman , KSHITIJ, Doshi A.
发明人： OULD-AHMED-VALL, Elmoustapha , YOUNT, Charles R. , SAIR, Suleyman , KSHITIJ, Doshi A.
IPC分类号： G06F9/30 , G06F9/305 , G06F9/06
CPC分类号： G06F9/30145 , G06F7/02 , G06F9/30018 , G06F9/30021 , G06F9/30036
摘要： Instructions and logic provide vector horizontal compare functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read values from data fields of the specified size in the source operand, corresponding to the mask and compare the values for equality. In some embodiments, responsive to a detection of inequality, a trap may be taken. In some alternative embodiments, a flag may be set. In other alternative embodiments, a mask field may be set to a masked state for the corresponding unequal value(s). In some embodiments, responsive to all unmasked data fields of the source operand being equal to a particular value, that value may be broadcast to all data fields of the specified size in the destination operand.
摘要翻译：指令和逻辑提供向量横向比较功能。一些实施例，响应于指定目的地操作数，向量元素的大小，源操作数和对应于源操作数中的向量元素数据字段的一部分的掩码的指令; 从源操作数中的指定大小的数据字段读取值，对应于掩码，并比较相等的值。在一些实施例中，响应于不等式的检测，可以采取陷阱。在一些替代实施例中，可以设置标志。在其他替代实施例中，可以将掩模字段设置为对应不等值的掩蔽状态。在一些实施例中，响应于源操作数的所有未屏蔽的数据字段等于特定值，该值可以广播到目的地操作数中指定大小的所有数据字段。

3. 发明申请

US20150095578A1 INSTRUCTIONS AND LOGIC TO PROVIDE MEMORY FENCE AND STORE FUNCTIONALITY 审中-公开
标题翻译：说明和逻辑提供记忆功能和存储功能
公开(公告)号：US20150095578A1
公开(公告)日：2015-04-02
申请号：US14040473
申请日：2013-09-27
申请人： Kshitij Doshi , Thomas Willhalm
发明人： Kshitij Doshi , Thomas Willhalm
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/0804 , G06F12/0875 , G06F12/0891
摘要： Instructions and logic provide memory fence and store functionality. Some embodiments include a processor having a cache to store cache coherent data in cache lines for one or more memory addresses of a primary storage. A decode stage of the processor decodes an instruction specifying a source data operand, one or more memory addresses as destination operands, and a memory fence type. Responsive to the decoded instruction, one or more execution units may enforce the memory fence type, then store data from the source data operand to the one or more memory addresses, and ensure that the stored data has been committed to primary storage. For some embodiments, the primary storage may comprise persistent memory. For some embodiments, cache lines corresponding to the memory addresses may be flushed, or marked for persistent write back to primary storage. Alternatively the cache may be bypassed, e.g. by performing a streaming vector store.
摘要翻译：说明和逻辑提供内存围栏和存储功能。一些实施例包括具有高速缓存以在主存储器的一个或多个存储器地址的高速缓存行中存储高速缓存相干数据的处理器。处理器的解码级将指定源数据操作数，一个或多个存储器地址作为目标操作数的指令和存储器栅栏类型进行解码。响应于解码的指令，一个或多个执行单元可以强制执行存储器栅栏类型，然后将来自源数据操作数的数据存储到一个或多个存储器地址，并确保存储的数据已被提交到主存储器。对于一些实施例，主存储器可以包括持久存储器。对于一些实施例，可以刷新对应于存储器地址的高速缓存行，或者标记用于持续写入主存储器。或者，可以绕过高速缓存。通过执行流媒体矢量存储。

4. 发明申请

US20190042219A1 TECHNIQUES FOR COMPILER SHELTERED NON-VOLATILE MEMORY STORES 审中-公开
公开(公告)号：US20190042219A1
公开(公告)日：2019-02-07
申请号：US16006404
申请日：2018-06-12
申请人： BHANU SHANKAR , KSHITIJ DOSHI
发明人： BHANU SHANKAR , KSHITIJ DOSHI
IPC分类号： G06F8/41
摘要： Various embodiments are generally directed to techniques for compiler sheltered nonvolatile memory (NVM) stores, such as based on demarcated atomic persistence regions in source code, for instance. Some embodiments are particularly related to a compiler that effectively shelters updates to NVM-based variables in a compiler implemented register, or register file, until the compiler has recorded undo values into a temporary but nonvolatile log range.

5. 发明申请

US20210117515A1 SOFTWARE DEFINED SILICON GUARDIANSHIP 有权
公开(公告)号：US20210117515A1
公开(公告)日：2021-04-22
申请号：US17133876
申请日：2020-12-24
申请人： Katalin Klara Bartfai-Walcott , Tamir Damian Munafo , Ghouse Adoni Mohammed , Kshitij Doshi , Haseeb Mohammed Abdul
发明人： Katalin Klara Bartfai-Walcott , Tamir Damian Munafo , Ghouse Adoni Mohammed , Kshitij Doshi , Haseeb Mohammed Abdul
IPC分类号： G06F21/10
摘要： Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) for software defined silicon guardianship are disclosed. An example method for semiconductor feature guardianship includes identifying, with a co-processor of a first semiconductor device, a feature based on a license received via a network from a remote enterprise system, the feature activated on a first semiconductor device based on the license, generating, with the co-processor of the first semiconductor device, a mesh network, the mesh network including a plurality of nodes associated with respective semiconductor devices including the first semiconductor device, the plurality of nodes including a primary node in communication with one or more secondary nodes, and migrating, with the co-processor of the first semiconductor device, the feature from a first secondary node to a second secondary node in response to a feature failure even on the first secondary node, the migration to maintain a feature entitlement associated with the license.

6. 发明申请

US20190044971A1 TECHNIQUES TO PROVIDE FUNCTION-LEVEL ISOLATION WITH CAPABILITY-BASED SECURITY 审中-公开
公开(公告)号：US20190044971A1
公开(公告)日：2019-02-07
申请号：US16024089
申请日：2018-06-29
申请人： VADIM SUKHOMLINOV , KSHITIJ DOSHI , MICHAEL LEMAY , DMITRY BABOKIN , AREG MELIK-ADAMYAN
发明人： VADIM SUKHOMLINOV , KSHITIJ DOSHI , MICHAEL LEMAY , DMITRY BABOKIN , AREG MELIK-ADAMYAN
IPC分类号： H04L29/06 , G06F21/57 , G06F9/455
摘要： Embodiments are directed toward techniques to detect a first function associated with an address space initiating a call instruction to a second function in the address space, the first function to call the second function in a deprivileged mode of operation, and define accessible address ranges for segments of the address space for the second function, each segment to a have a different address range in the address space where the second function is permitted to access in the deprivileged mode of operation, Embodiments include switching to the stack associated with the second address space and the second function, and initiating execution of the second function in the deprivileged mode of operation

7. 发明申请

US20070289006A1 CROSS DOMAIN AUTHENTICATION AND SECURITY SERVICES USING PROXIES FOR HTTP ACCESS 有权
标题翻译：使用代码进行HTTP访问的跨域认证和安全服务
公开(公告)号：US20070289006A1
公开(公告)日：2007-12-13
申请号：US11843287
申请日：2007-08-22
申请人： Viyyokaran RAMACHANDRAN , Dinkar SITARAM , Kshitij DOSHI
发明人： Viyyokaran RAMACHANDRAN , Dinkar SITARAM , Kshitij DOSHI
IPC分类号： H04L9/32 , G06F15/16 , G06F17/00
CPC分类号： H04L63/08 , H04L9/321 , H04L9/3263 , H04L9/3271 , H04L63/101 , H04L2209/76
摘要： Two identity spaces form a federation by agreeing to use a secret key to facilitate secure access of resources between them. When one identity space receives a request for a resource from a user in the other identity space, the first identity space checks to see if the resource is protected. If the resource is protected, the first identity space requests that a mediator in the second identity space authenticate the external user. The mediator verifies the external user's authenticity. Once the external user is authenticated, the mediator securely informs the first identity space, using the secret key, that the external user is authenticated to access the resource. The identity space then grants the user access to the resource if the user is allowed access as per the access control policy of the identity space.
摘要翻译：两个身份空间通过同意使用秘密密钥来促进他们之间资源的安全访问，形成联盟。当一个身份空间从另一身份空间中的用户接收到对资源的请求时，第一身份空间将检查资源是否受保护。如果资源受到保护，则第一身份空间请求第二个身份空间中的中介器验证外部用户。调解员验证外部用户的真实性。一旦对外部用户进行了身份验证，中介者使用秘密密钥安全地通知第一个身份空间，认证外部用户访问该资源。如果根据身份空间的访问控制策略允许用户访问，身份空间则授予用户对资源的访问权限。

8. 发明申请

US20070186055A1 Technique for using memory attributes 有权
标题翻译：使用内存属性的技术
公开(公告)号：US20070186055A1
公开(公告)日：2007-08-09
申请号：US11349661
申请日：2006-02-07
申请人： Quinn Jacobson , Anne Bracy , Hong Wang , John Shen , Per Hammarlund , Matthew Merten , Suresh Srinivas , Kshitij Doshi , Gautham Chinya , Bratin Saha , Ali-Reza Adl-Tabatabai , Gad Sheaffer
发明人： Quinn Jacobson , Anne Bracy , Hong Wang , John Shen , Per Hammarlund , Matthew Merten , Suresh Srinivas , Kshitij Doshi , Gautham Chinya , Bratin Saha , Ali-Reza Adl-Tabatabai , Gad Sheaffer
IPC分类号： G06F13/28
CPC分类号： G06F12/0815 , G06F11/3471 , G06F11/3648 , G06F12/0804 , G06F12/0817 , G06F12/0831 , G06F12/0842 , G06F12/145 , G06F2201/865
摘要： A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.
摘要翻译：使用存储器属性将信息中继到程序或其他代理的技术。更具体地，本发明的实施例涉及使用存储器属性位以有效的方式检查各种存储器特性。

9. 发明申请

US20190324911A1 REMOTE MEMORY OPERATIONS FOR COMPUTING SYSTEMS WITH SHARED MEMORY 审中-公开
公开(公告)号：US20190324911A1
公开(公告)日：2019-10-24
申请号：US16457826
申请日：2019-06-28
申请人： Kshitij Doshi , Harald Servat , Francesc Guim Bernat
发明人： Kshitij Doshi , Harald Servat , Francesc Guim Bernat
IPC分类号： G06F12/0831 , G06F12/0842 , G06F9/54
摘要： Embodiments may include systems and methods for performing remote memory operations in a shared memory address space. An apparatus includes a first network controller coupled to a first processor core. The first network controller processes a remote memory operation request, which is generated by a first memory coherency agent based on a first memory operation for an application operating on the first processor core. The remote memory operation request is associated with a remote memory address that is local to a second processor core coupled to the first processor core. The first network controller forwards the remote memory operation request to a second network controller coupled to the second processor core. The second processor core and the second network controller are to carry out a second memory operation to extend the first memory operation as a remote memory operation. Other embodiments may be described and/or claimed.

10. 发明申请

US20190034206A1 TECHNIQUES TO MITIGATE HIGH LATENCY INSTRUCTIONS IN HIGH FREQUENCY EXECUTION PATHS 审中-公开
公开(公告)号：US20190034206A1
公开(公告)日：2019-01-31
申请号：US15825183
申请日：2017-11-29
申请人： Harshad Sane , Kshitij Doshi
发明人： Harshad Sane , Kshitij Doshi
IPC分类号： G06F9/38 , G06F11/34 , G06F9/30
摘要： Embodiments may be directed to techniques to execute a binary based on source code comprising basic blocks of instructions, identify a path of execution of a plurality of the basic blocks of instructions having a higher execution frequency than an execution frequency threshold, and collect last branch records for the plurality of the basic blocks of instructions, the last branch records to indicate times of execution for the plurality of the basic blocks of instructions. Further, embodiments include determining latency values for each of the plurality of the basic blocks of instructions based on the times of execution, and performing a mitigation operation for each of the plurality of the basic blocks of instruction having latency values above a latency threshold.

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