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1. 发明授权

US08811470B2 Integrated circuit for video/audio processing 有权
标题翻译：用于视频/音频处理的集成电路
公开(公告)号：US08811470B2
公开(公告)日：2014-08-19
申请号：US10599494
申请日：2005-04-01
申请人： Kozo Kimura , Tokuzo Kiyohara , Hiroshi Mizuno , Junji Michiyama , Tomohiko Kitamura , Ryoji Yamaguchi , Manabu Kuroda , Nobuhiko Yamada , Hideyuki Ohgose , Akifumi Yamana
发明人： Kozo Kimura , Tokuzo Kiyohara , Hiroshi Mizuno , Junji Michiyama , Tomohiko Kitamura , Ryoji Yamaguchi , Manabu Kuroda , Nobuhiko Yamada , Hideyuki Ohgose , Akifumi Yamana
IPC分类号： H04N7/12
CPC分类号： G06F13/4027 , H04N5/775 , H04N5/781 , H04N5/85 , H04N5/907 , H04N9/7921 , H04N9/8042
摘要： An integrated circuit for video/audio processing in which design resources obtained by development of video/audio devices can also be used for other types of video/audio devices. The integrated circuit includes a microcomputer that includes a CPU, a stream input/output for inputting/outputting a video and audio stream to and from an external device, a media processor that executes the media processing including at least one compressing and decompressing the video and audio stream inputted to the stream input/output, an AV input/output that converts the video and audio stream subjected to the media processing by the media processor into video and audio signals and outputting these signals to the external device. A memory interface controls a data transfer between the microcomputer, the stream input/output, the media processor and the AV input/output and an external memory.
摘要翻译：用于视频/音频处理的集成电路，其中通过开发视频/音频设备获得的设计资源也可以用于其他类型的视频/音频设备。集成电路包括微型计算机，其包括CPU，用于向外部设备输入/输出视频和音频流的流输入/输出，执行媒体处理的媒体处理器，该媒体处理包括至少一个压缩和解压缩视频，以及输入到流输入/输出的音频流，将由媒体处理器进行媒体处理的视频和音频流转换成视频和音频信号并将这些信号输出到外部设备的AV输入/输出。存储器接口控制微机，流输入/输出，媒体处理器和AV输入/输出之间的数据传输以及外部存储器。

2. 发明申请

US20110283288A1 PROCESSOR AND PROGRAM EXECUTION METHOD CAPABLE OF EFFICIENT PROGRAM EXECUTION 有权
标题翻译：能够有效执行计划的执行者和计划执行方法
公开(公告)号：US20110283288A1
公开(公告)日：2011-11-17
申请号：US13179614
申请日：2011-07-11
申请人： KAZUSHI KURATA , TETSUYA TANAKA , NOBUO HIGAKI , KUNIHIKO HAYASHI , HIROSHI KADOTA , TOKUZO KIYOHARA , KOZO KIMURA , HIDESHI NISHIDA , KAZUYA FURUKAWA , SHIGEKI FUJII , TOSHIO SUGIMURA
发明人： KAZUSHI KURATA , TETSUYA TANAKA , NOBUO HIGAKI , KUNIHIKO HAYASHI , HIROSHI KADOTA , TOKUZO KIYOHARA , KOZO KIMURA , HIDESHI NISHIDA , KAZUYA FURUKAWA , SHIGEKI FUJII , TOSHIO SUGIMURA
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/3867 , G06F9/462
摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.
摘要翻译：一种处理器，用于使用存储在与所述程序一对一的存储器中的多个寄存器值组来顺序地执行多个程序。处理器包括多个寄存器组; 选择/切换单元，其可操作以选择所述多个寄存器组中的一个作为程序执行所基于的执行目标寄存器组，并且每当经过第一预定时间时切换所述选择目标; 恢复单元，其可操作以在每次执行切换时将所述寄存器值组中的一个恢复为未被选择为所述执行目标寄存器组的寄存器组之一; 保存单元，其可操作以通过重写与寄存器值相对应的存储器中的寄存器值组来在恢复之前保存用于恢复的寄存器组中的值; 以及程序执行单元，其可操作以在每次执行切换时执行与执行目标寄存器组中的寄存器值组相对应的程序。

3. 发明授权

US07921281B2 Processor and program execution method capable of efficient program execution 有权
标题翻译：处理器和程序执行方法能够高效地执行程序
公开(公告)号：US07921281B2
公开(公告)日：2011-04-05
申请号：US12110513
申请日：2008-04-28
申请人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
发明人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
IPC分类号： G06F9/48 , G06F9/52
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/3867 , G06F9/462
摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.
摘要翻译：一种处理器，用于使用存储在与所述程序一对一的存储器中的多个寄存器值组来顺序地执行多个程序。处理器包括多个寄存器组; 选择/切换单元，其可操作以选择所述多个寄存器组中的一个作为程序执行所基于的执行目标寄存器组，并且每当经过第一预定时间时切换所述选择目标; 恢复单元，其可操作以在每次执行切换时将所述寄存器值组中的一个恢复为未被选择为所述执行目标寄存器组的寄存器组之一; 保存单元，其可操作以通过重写与寄存器值相对应的存储器中的寄存器值组来在恢复之前保存用于恢复的寄存器组中的值; 以及程序执行单元，其可操作以在每次执行切换时执行与执行目标寄存器组中的寄存器值组相对应的程序。

4. 发明申请

US20080209162A1 PROCESSOR AND PROGRAM EXECUTION METHOD CAPABLE OF EFFICIENT PROGRAM EXECUTION 有权
公开(公告)号：US20080209162A1
公开(公告)日：2008-08-28
申请号：US12110491
申请日：2008-04-28
申请人： Kazuya Furukawa , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazushi Kurata , Shigeki Fujii , Toshio Sugimura
发明人： Kazuya Furukawa , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazushi Kurata , Shigeki Fujii , Toshio Sugimura
IPC分类号： G06F9/30
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/3867 , G06F9/462
摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

5. 发明授权

US07020787B2 Microprocessor 失效
公开(公告)号：US07020787B2
公开(公告)日：2006-03-28
申请号：US10323419
申请日：2002-12-18
申请人： Satoshi Takashima , Hideshi Nishida , Kozo Kimura , Tokuzo Kiyohara
发明人： Satoshi Takashima , Hideshi Nishida , Kozo Kimura , Tokuzo Kiyohara
IPC分类号： G06F1/32
CPC分类号： G06F9/30014 , G06F7/57
摘要： A microprocessor comprises a calculation unit that (i) includes partial calculation units each operable to perform partial data calculation, and (ii) is operable to perform data calculation on N or less bits, where N is a total number of bits on which the partial calculation units are to perform data calculation. The microprocessor, when having the calculation unit perform data calculation according to an instruction fetched from a memory, controls the partial calculation units depending on a bit width mode selected in terms of a number of bits on which data calculation is to be performed, so as to either (i) have all the partial calculation units operate, or (ii) suspend operation of a predetermined number of the partial calculation units, and have the rest of the partial calculation units operate.

6. 发明申请

US20050102440A1 Circuit group control system 审中-公开
公开(公告)号：US20050102440A1
公开(公告)日：2005-05-12
申请号：US11009607
申请日：2004-12-08
申请人： Nobuo Higaki , Tetsuya Tanaka , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura
发明人： Nobuo Higaki , Tetsuya Tanaka , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura
IPC分类号： G06F9/38 , G06F3/00 , G06F9/46 , G06F9/48 , G06F13/28 , G06F15/16 , G06F15/167 , G06F15/80
CPC分类号： G06F9/4843
摘要： A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.

7. 发明授权

US5535358A Cache memory control circuit and method for controlling reading and writing requests 失效
标题翻译：缓存存储器控制电路和控制读写请求的方法
公开(公告)号：US5535358A
公开(公告)日：1996-07-09
申请号：US364277
申请日：1994-12-27
申请人： Kozo Kimura , Tokuzo Kiyohara
发明人： Kozo Kimura , Tokuzo Kiyohara
IPC分类号： G06F12/08 , G06F12/00 , G06F12/02 , G06F13/00
CPC分类号： G06F12/0859
摘要： In cases where a remarked unit of tag addresses set in effective or access state is not registered in a tag section when a reading request is input, an external access is performed, and the remarked unit of tag addresses and other units of tag addresses respectively set in the access state are prepared in a tag entry preparing unit. In cases where a writing request is input to write a piece of updated word data in a remarked unit of data addresses corresponding to the remarked unit of tag addresses before the external access is finished, the state of the remarked tag entry prepared is changed to the effective state, and the updated word data is written in the remarked unit of data addresses of a data storing unit. Because the remarked unit of tag addresses is set in the effective state, the updated word data written in the remarked unit of data addresses is not replaced with a piece of external word data obtained according to the external access when the external access is finished. In cases where any writing request is not input until the external access is finished, the external word data is written in the remarked unit of data addresses, and the state of the remarked unit of tag addresses is changed to the effective state to replace the external word data with a piece of updated word data relating to a following writing request. Therefore, the writing and reading requests can be performed without delaying the writing request.
摘要翻译：在输入了读取请求时，标签地址设定为有效或访问状态的注释单位未登记在标签区域的情况下，执行外部访问，并且标记地址的标记单位和标签地址的其他单位分别设定在访问状态下，在标签输入准备单元中准备。在外部访问完成之前输入写入请求以写入与标记地址的标记单元相对应的数据地址的注释单元中的更新字数据的情况下，准备的标记标签条目的状态被改变为并且更新的字数据被写入数据存储单元的数据地址的标记单元中。由于标记地址的标记单位被设置为有效状态，所以在外部访问完成时，写入数据地址的注释单元中的更新后的字数据不被替换为根据外部访问获得的外部字数据。在外部访问完成之前没有输入任何写入请求的情况下，将外部字数据写入数据地址的注释单元，并将标记地址的标记单元的状态改变为有效状态以替换外部字具有与以下写入请求有关的更新的字数据的字数据。因此，可以在不延迟写入请求的情况下执行写入和读取请求。

8. 发明授权

US4185930A Print position control in a printer including a printer head mounted on a traveling carriage 失效
标题翻译：打印机中的打印位置控制，包括安装在行驶台上的打印头
公开(公告)号：US4185930A
公开(公告)日：1980-01-29
申请号：US918419
申请日：1978-06-23
申请人： Ikuo Umeda , Masahiko Aiba , Kozo Kimura
发明人： Ikuo Umeda , Masahiko Aiba , Kozo Kimura
IPC分类号： G06K15/00 , B41J19/18 , B41J19/20 , B41J19/30 , B41J25/22
CPC分类号： B41J19/202
摘要： A printer head is mounted on a carriage which is driven to travel in the row direction at a predetermined constant speed. A pulse generation device is provided for developing a pulse signal in response to the travel of the carriage in order to determine print width. A detection device develops a detection signal when the carriage reaches the first print position to initiate printing of the first character. The detection signal is applied to a counter which counts a time interval from a time at which the last pulse is developed from the pulse generation device to a time at which the detection signal is developed. The following character printing is effected each time the pulse generation device develops a predetermined number of pulses indicative of one character width or print pitch and the time interval determined by the counter has passed from the time at which the last pulse of the predetermined number is developed.
摘要翻译：打印机头安装在滑架上，该滑架被驱动以预定的恒定速度在行方向上行进。脉冲发生装置被提供用于响应于滑架的移动而形成脉冲信号，以便确定打印宽度。当托架到达第一打印位置时，检测装置产生检测信号以开始打印第一个字符。检测信号被施加到计数器，该计数器从最后脉冲从脉冲发生装置发展的时间到检测信号被显影的时间计数一个时间间隔。每当脉冲发生装置产生指示一个字符宽度或打印间距的预定数量的脉冲并且由计数器确定的时间间隔从预定数量的最后脉冲开始的时间已经过去时，进行以下字符打印。

9. 发明授权

US08082429B2 Information processing apparatus and exception control circuit 有权
标题翻译：信息处理装置和异常控制电路
公开(公告)号：US08082429B2
公开(公告)日：2011-12-20
申请号：US13052281
申请日：2011-03-21
申请人： Hideshi Nishida , Takeshi Furuta , Tetsuya Tanaka , Kozo Kimura , Tokuzo Kiyohara
发明人： Hideshi Nishida , Takeshi Furuta , Tetsuya Tanaka , Kozo Kimura , Tokuzo Kiyohara
IPC分类号： G06F9/48
CPC分类号： G06F13/24 , G06F9/30101 , G06F9/3861 , G06F9/3879 , G06F9/4812 , G06F2209/481
摘要： An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor; a data processing unit that performs particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue an interrupt request to execute an exception handler to the processor.
摘要翻译：信息处理装置执行异常处理程序与正常处理之间的切换。信息处理装置包括：处理器; 数据处理单元，在从所述处理器接收到处理请求时执行特定处理; 一个向处理器发出中断请求的中断控制器; 以及异常控制单元，其控制所述中断控制器，其中所述数据处理单元经由专用线与所述异常控制单元连接。数据处理单元包括：通知单元，其经由专用线通知异常控制单元，该异常控制单元指示数据处理单元的当前状态的状态信息，并且基于所通知的状态信息和由处理器设置的设置信息，异常控制单元判断是否使中断控制器发出中断请求以对处理器执行异常处理程序。

10. 发明申请

US20110173361A1 INFORMATION PROCESSING APPARATUS AND EXCEPTION CONTROL CIRCUIT 有权
标题翻译：信息处理设备和异常控制电路
公开(公告)号：US20110173361A1
公开(公告)日：2011-07-14
申请号：US13052281
申请日：2011-03-21
申请人： Hideshi Nishida , Takeshi Furuta , Tetsuya Tanaka , Kozo Kimura , Tokuzo Kiyohara
发明人： Hideshi Nishida , Takeshi Furuta , Tetsuya Tanaka , Kozo Kimura , Tokuzo Kiyohara
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F9/30101 , G06F9/3861 , G06F9/3879 , G06F9/4812 , G06F2209/481
摘要： An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor; a data processing unit that performs particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue an interrupt request to execute an exception handler to the processor.
摘要翻译：信息处理装置执行异常处理程序与正常处理之间的切换。信息处理装置包括：处理器; 数据处理单元，在从所述处理器接收到处理请求时执行特定处理; 一个向处理器发出中断请求的中断控制器; 以及异常控制单元，其控制所述中断控制器，其中所述数据处理单元经由专用线与所述异常控制单元连接。数据处理单元包括：通知单元，其经由专用线通知异常控制单元，该异常控制单元指示数据处理单元的当前状态的状态信息，并且基于所通知的状态信息和由处理器设置的设置信息，异常控制单元判断是否使中断控制器发出中断请求以对处理器执行异常处理程序。

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