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1. 发明授权

US06425040B1 LAN docker unlocking system 失效
标题翻译： LAN码头解锁系统
公开(公告)号：US06425040B1
公开(公告)日：2002-07-23
申请号：US09324547
申请日：1999-06-02
申请人： Koichi Dewa , Toru Hanada , Makoto Kosaka
发明人： Koichi Dewa , Toru Hanada , Makoto Kosaka
IPC分类号： G06F1300
CPC分类号： G06F1/1632 , G06F1/3203
摘要： When a PC main body wakes up, docking condition discrimination for checking if a LAN controller can be used is made. If the docking condition is satisfied, the LAN controller is set in an operative state, and the PC main body is used while being locked by a lock mechanism. When the WOL function is enabled, a signal WOLEN is activated. In this state, even when the PC main body goes to a sleep state and a signal DOCPWON is turned off, the LAN controller is kept powered. In this case, since the lock mechanism is unlocked, the user can immediately detach the PC main body from a LAN docker and can carry it to a location of his or her choice.
摘要翻译： PC主机唤醒时，进行对接状态判别，以检查是否可以使用LAN控制器。如果对接条件满足，则LAN控制器被设置为操作状态，并且PC主体在被锁定机构锁定的同时被使用。当WOL功能使能时，信号WOLEN被激活。在这种状态下，即使PC主体进入睡眠状态并且信号DOCPWON被关闭，LAN控制器被保持供电。在这种情况下，由于锁定机构被解锁，用户可以立即将PC主体从LAN码头拆下并将其携带到他或她选择的位置。

2. 发明授权

US5522076A Computer system having BIOS (basic input/output system)-ROM (Read Only Memory) writing function 失效
标题翻译：具有BIOS（基本输入/输出系统）-ROM（只读存储器）写入功能的计算机系统
公开(公告)号：US5522076A
公开(公告)日：1996-05-28
申请号：US234475
申请日：1994-04-28
申请人： Koichi Dewa , Kyoji Hayashi , Shigeru Satake
发明人： Koichi Dewa , Kyoji Hayashi , Shigeru Satake
IPC分类号： G06F9/445 , G06F11/14 , G06F9/44
CPC分类号： G06F9/4406 , G06F8/665 , G06F11/1417
摘要： A flash memory used as a BIOS-ROM has a main block storing a BIOS and a boot block storing minimum programs executed in initializing the system. Upon a power-on operation, when a rewriting unit is connected to an expansion bus connector, a new boot block stored in a ROM of the rewriting unit is written in the flash memory. Upon the power-on operation, a key depression detecting routine in the boot block is executed to check whether a predetermined key is depressed. If the predetermined key is determined to be depressed, a rewriting program in a floppy disk is loaded in the system and executed, thereby rewriting the content of the main block into the BIOS file stored in the floppy disk.
摘要翻译：用作BIOS-ROM的闪速存储器具有存储BIOS的主块和存储在初始化系统中执行的最小程序的引导块。在通电操作时，当重写单元连接到扩展总线连接器时，存储在重写单元的ROM中的新引导块被写入闪存。在通电操作时，执行引导块中的按键检测程序以检查预定键是否被按下。如果确定预定键被按下，则将软盘中的重写程序加载到系统中并执行，从而将主块的内容重新写入存储在软盘中的BIOS文件。

3. 发明授权

US5475762A Computer with password processing function and password processing method of computer 失效
标题翻译：具有密码处理功能的计算机和计算机的密码处理方法
公开(公告)号：US5475762A
公开(公告)日：1995-12-12
申请号：US218296
申请日：1994-03-28
申请人： Toshikazu Morisawa , Koichi Dewa , Toshimitsu Saito
发明人： Toshikazu Morisawa , Koichi Dewa , Toshimitsu Saito
IPC分类号： G06F21/31 , H04L9/32 , G06F13/14
CPC分类号： G06F21/31
摘要： A computer has a conversion module for converting a password to be registered into a compressed-bit row in accordance with a predetermined rule. A registration module stores the compressed bit row of the registered password in a backup RAM. A conversion module converts a password to be compared with the registered password into a compressed bit row. A comparison module compares the compressed bit row of the compared password with the compressed bit row of the registered password. Upon detecting a coincidence between the two compressed bit rows, a system activation module is activated to set the system to a access allowable state.
摘要翻译：计算机具有转换模块，用于根据预定规则将要注册的口令转换成压缩比特行。注册模块将注册密码的压缩位行存储在备份RAM中。转换模块将要与注册密码进行比较的密码转换为压缩位行。比较模块将比较密码的压缩位行与注册密码的压缩位行进行比较。当检测到两个压缩位行之间的一致时，启动系统激活模块以将系统设置为访问允许状态。

4. 发明授权

US5113497A I/O control system for a plurality of peripheral devices 失效
标题翻译：用于大量外围设备的I / O控制系统
公开(公告)号：US5113497A
公开(公告)日：1992-05-12
申请号：US664520
申请日：1991-03-05
申请人： Koichi Dewa
发明人： Koichi Dewa
IPC分类号： G06F13/10 , G06F3/06 , G06F13/38
CPC分类号： G06F3/0601 , G06F13/385 , G06F2003/0692
摘要： A basic input and output system program, (BIOS) includes a 16-bit interface hard disk controller, (HDC) control routine and an 8-bit interface HDC control routine, and also includes an automatic HDC type determination routine. The 16-bit interface HDC has an inherent I/O address (I/O port), but the 8-bit interface HDC has no inherent I/O address (I/O port). By utilizing this fact, a CPU writes specified data at the I/O address inherent to the 16-bit interface HDC. The CPU then reads out the data from the I/O address, and compares the read data with the written data. If a coincidence is obtained, the CPU determines that the 16-bit interface HDC is used, and sets up a 16-bit interface HDC control routine. On the other hand, if no coincidence is obtained, the CPU determines that the 8-bit interface HDC is used, and sets up an 8-bit interface HDC control routine.

5. 发明授权

US4644418A Floppy disk control apparatus 失效
标题翻译：软盘控制装置
公开(公告)号：US4644418A
公开(公告)日：1987-02-17
申请号：US620622
申请日：1984-06-14
申请人： Haruhiko Banno , Koichi Dewa
发明人： Haruhiko Banno , Koichi Dewa
IPC分类号： G11B20/10 , G06F3/06 , G11B5/016 , G11B20/12 , G11B5/09
CPC分类号： G06F3/0607 , G06F3/0659 , G06F3/0676 , G11B20/1252 , G11B5/016 , G11B20/1217 , G11B2020/1087 , G11B2020/10916 , G11B2220/2508 , G11B2220/2512
摘要： When a FORMAT COMMAND is executed, a track density data indicating a track density of 96 TPI or 48 TPI is written into a discrimination area of a disk. When the disk is set into the FDD and is used, a CPU reads out track density data from the disk and produces a flag byte data, including the track density data, and stores it into a main memory. When SEEK COMMAND is executed, a track density of the disk is checked to see if it is 96 TPI or 48 TPI on the basis of the flag byte data. If it is determined that the disk of 48 TPI is set into the FDD for use in driving a disk of 96 TPI according to this discrimination, an FDC outputs a STEP signal for allowing the traveling distance of the head to be doubled as compared to an ordinary distance, thereby controlling the seeking operation by the FDD so as to assuredly move the head to a predetermined desired track.
摘要翻译：当执行格式命令时，将指示轨道密度为96TPI或48TPI的轨道密度数据写入盘的识别区域。当磁盘被设置为FDD并被使用时，CPU从盘读出磁道密度数据，并产生包括磁道密度数据的标志字节数据，并将其存储到主存储器中。执行SEEK COMMAND时，根据标志字节数据检查磁盘的磁道密度，以查看其是否为96 TPI或48 TPI。如果根据这种鉴别确定将48TPI的盘设置为用于驱动96TPI的盘的FDD中，则FDC输出STEP信号，以允许头的行进距离加倍从而通过FDD控制寻道操作，以便确保将头移动到预定的所需轨道。

6. 发明授权

US06230279B1 System and method for dynamically controlling processing speed of a computer in response to user commands 有权
标题翻译：响应于用户命令动态地控制计算机的处理速度的系统和方法
公开(公告)号：US06230279B1
公开(公告)日：2001-05-08
申请号：US09563820
申请日：2000-05-03
申请人： Koichi Dewa , Masayo Yamaki , Fumitaka Sato
发明人： Koichi Dewa , Masayo Yamaki , Fumitaka Sato
IPC分类号： G06F132
CPC分类号： G06F1/324 , G06F1/3203 , G06F9/30181 , G06F9/3804 , G06F9/3844 , Y02D10/126
摘要： When a user instructs acceleration or deceleration of the CPU processing speed with an “accelerator” button or a “brake” button, a speed control MMI informs power management system software of the corresponding information to change the CPU processing speed. The change is recorded on a speed management database in correspondence with the name of the application program which is currently being executed. Every time acceleration or deceleration of the CPU processing speed is instructed by the user, speed management data is formed on the speed management database. By using the speed management data, the CPU processing speed can be dynamically controlled for each piece of software when it is executed. Further disclosed is a novel power dissipation control system for a microprocessor, adapted to be used in conjunction with the above described MMI.
摘要翻译：当用户通过“加速器”按钮或“制动”按钮指示CPU处理速度的加速或减速时，速度控制MMI向电源管理系统软件通知相应信息以改变CPU处理速度。该变更与当前正在执行的应用程序的名称对应地记录在速度管理数据库中。每当由用户指示CPU处理速度的加速或减速时，速度管理数据形成在速度管理数据库上。通过使用速度管理数据，可以在执行时对每个软件动态地控制CPU处理速度。进一步公开了一种用于微处理器的新型功率耗散控制系统，适用于与上述MMI结合使用。

7. 发明授权

US6081901A System and method for dynamically controlling processing speed of a computer in response to user commands 失效
标题翻译：响应于用户命令动态地控制计算机的处理速度的系统和方法
公开(公告)号：US6081901A
公开(公告)日：2000-06-27
申请号：US73808
申请日：1998-05-07
申请人： Koichi Dewa , Masayo Yamaki , Fumitaka Sato
发明人： Koichi Dewa , Masayo Yamaki , Fumitaka Sato
IPC分类号： G06F3/14 , G06F1/04 , G06F1/32 , G06F3/048 , G06F9/38 , G06F1/08
CPC分类号： G06F1/324 , G06F1/3203 , G06F9/30181 , G06F9/3804 , G06F9/3844 , Y02B60/1217
摘要： When a user instructs acceleration or deceleration of the CPU processing speed with an "accelerator" button or a "brake" button, a speed control MMI informs power management system software of the corresponding information to change the CPU processing speed. The change is recorded on a speed management database in correspondence with the name of the application program which is currently being executed. Every time acceleration or deceleration of the CPU processing speed is instructed by the user, speed management data is formed on the speed management database. By using the speed management data, the CPU processing speed can be dynamically controlled for each piece of software when it is executed. Further disclosed is a novel power dissipation control system for a microprocessor, adapted to be used in conjunction with the above described MMI.
摘要翻译：当用户通过“加速器”按钮或“制动”按钮指示CPU处理速度的加速或减速时，速度控制MMI向电源管理系统软件通知相应信息以改变CPU处理速度。该变更与当前正在执行的应用程序的名称对应地记录在速度管理数据库中。每当由用户指示CPU处理速度的加速或减速时，速度管理数据形成在速度管理数据库上。通过使用速度管理数据，可以在执行时对每个软件动态地控制CPU处理速度。进一步公开了一种用于微处理器的新型功率耗散控制系统，适用于与上述MMI结合使用。

8. 发明授权

US5613135A Portable computer having dedicated register group and peripheral controller bus between system bus and peripheral controller 失效
标题翻译：便携式计算机具有专用寄存器组和系统总线与外设控制器之间的外设控制器总线
公开(公告)号：US5613135A
公开(公告)日：1997-03-18
申请号：US106724
申请日：1993-08-16
申请人： Makoto Sakai , Koichi Dewa , Hiroyuki Tsukada , Keiichi Uehara , Tohru Mamata , Yasuhiro Nishino , Hiroyuki Oda
发明人： Makoto Sakai , Koichi Dewa , Hiroyuki Tsukada , Keiichi Uehara , Tohru Mamata , Yasuhiro Nishino , Hiroyuki Oda
IPC分类号： G06F1/16 , G06F1/26 , G06F1/28 , G06F1/32 , G06F3/023 , G06F13/42 , G06F3/00
CPC分类号： G06F1/165 , G06F1/1616 , G06F1/1677 , G06F1/26 , G06F1/28 , G06F1/3218 , G06F13/4226 , G06F3/023
摘要： Dedicated registers are arranged in a status LCD control gate array connected to a system bus, and the dedicated registers or register group and a keyboard controller are connected through a keyboard interface bus. The keyboard controller has two ports for communicating with a CPU. The keyboard controller transfers existing commands released to an application program or the like and transmits normal key data through the system bus. The keyboard controller transmits hot key data and transfers a command for realizing any other special function through the keyboard interface bus and the dedicated registers.
摘要翻译：专用寄存器布置在连接到系统总线的状态LCD控制门阵列中，专用寄存器或寄存器组和键盘控制器通过键盘接口总线连接。键盘控制器有两个用于与CPU通信的端口。键盘控制器将释放的现有命令传送到应用程序等，并通过系统总线发送普通密钥数据。键盘控制器通过键盘接口总线和专用寄存器传送热键数据并传送用于实现任何其他特殊功能的命令。

9. 发明授权

US5278958A Method and apparatus for selecting a keyboard on a computer system 失效
标题翻译：用于在计算机系统上选择键盘的方法和装置
公开(公告)号：US5278958A
公开(公告)日：1994-01-11
申请号：US662999
申请日：1991-02-28
申请人： Koichi Dewa
发明人： Koichi Dewa
IPC分类号： G06F3/02 , G06F3/023 , G06F3/04
CPC分类号： G06F3/0227 , G06F3/023
摘要： The selection of a keyboard on a computer system can automatically be achieved. If any externally provided keyboard which transmits transmission data upon the turning on of a computer system is connected to an external keyboard controller, a selection circuit selects that external keyboard controller for controlling the externally provided keyboard. If, on the other hand, no externally provided keyboard is connected to the external keyboard controller, the selection circuit selects an incorporated keyboard controller for controlling an incorporated keyboard which is incorporated in the computer system. When the externally provided keyboard is connected to the external keyboard controller, the selection of a keyboard by the selection circuit is achieved depending upon whether or not the computer system receives transmission data from the externally provided keyboard.
摘要翻译：可以自动实现计算机系统上的键盘选择。如果在计算机系统接通时传输传输数据的任何外部提供的键盘连接到外部键盘控制器，则选择电路选择外部键盘控制器来控制外部提供的键盘。另一方面，如果没有外部提供的键盘连接到外部键盘控制器，则选择电路选择并入的键盘控制器来控制结合在计算机系统中的并入的键盘。当外部提供的键盘连接到外部键盘控制器时，根据计算机系统是否从外部提供的键盘接收传输数据来实现由选择电路选择键盘。

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