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1. 发明授权

US08432735B2 Memory system and related method of programming 有权
标题翻译：内存系统和相关的编程方法
公开(公告)号：US08432735B2
公开(公告)日：2013-04-30
申请号：US12832220
申请日：2010-07-08
申请人： Yong June Kim , Jae hong Kim , Ki jun Lee
发明人： Yong June Kim , Jae hong Kim , Ki jun Lee
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C7/1012 , G11C11/5642 , G11C2211/5647
摘要： A method of programming a nonvolatile memory device comprises counting a number of state pairs in a unit of input data, modulating the unit of input data to reduce the number of state pairs contained therein, and programming the modulated unit of input data in the nonvolatile memory device. Each state pair comprises data with a first state and designated for programming in a memory cell connected to a first word line, and data with a second state and designated for programming in a memory cell connected to a second word line adjacent to the first word line. The memory cell connected to the first word line is adjacent to the memory cell connected to the second word line.
摘要翻译：一种对非易失性存储器件进行编程的方法包括以输入数据为单位对多个状态对进行计数，调制输入数据的单位以减少其中包含的状态对的数量，并将输入数据的调制单元编程在非易失性存储器设备。每个状态对包括具有第一状态并被指定用于在连接到第一字线的存储器单元中进行编程的数据，以及具有第二状态并被指定用于在连接到与第一字线相邻的第二字线的存储器单元中编程的数据。连接到第一字线的存储单元与连接到第二字线的存储单元相邻。

2. 发明申请

US20110208566A1 Sales management system using a character recognition technique, and sales management method using same 审中-公开
标题翻译：销售管理系统采用字符识别技术，并采用销售管理方式
公开(公告)号：US20110208566A1
公开(公告)日：2011-08-25
申请号：US12921194
申请日：2009-11-11
申请人： Ki Jun Lee
发明人： Ki Jun Lee
IPC分类号： G06Q10/00
CPC分类号： G06Q30/06 , G06Q10/06393
摘要： The present invention relates to a sales management system using a text recognition technique, including a business card input device for inputting a business card of a customer; a text recognition server for recognizing and classifying information of the inputted business card; a customer database (DB) for storing the classified information; a sales process presentation server for fetching the information from the customer DB and presenting each step of a sales process corresponding to the retrieved information; a sales management server for, when the steps of the sales process presented by the sales process presentation server are selected, sequentially performing the steps and storing a result of the execution in a result DB; an obstacle factor DB for storing reasons for which the sales process is not sequentially performed in the sales management server; the result DB for storing a sales management result; a result report server for transmitting the sales management result, stored in the result DB, to a superior terminal; and a superior terminal for receiving a report on the sales management result and writing an opinion on the sales management result.
摘要翻译：本发明涉及一种使用文本识别技术的销售管理系统，包括用于输入客户名片的名片输入装置; 用于识别和分类所输入的名片的信息的文本识别服务器; 用于存储分类信息的客户数据库（DB）; 销售处理呈现服务器，用于从客户DB获取信息，并呈现与所检索信息相对应的销售过程的每个步骤; 销售管理服务器，当选择由销售处理呈现服务器呈现的销售过程的步骤时，顺序执行步骤并将执行结果存储在结果DB中; 用于存储在销售管理服务器中不顺序执行销售处理的原因的障碍因子DB; 用于存储销售管理结果的结果DB; 用于将存储在结果DB中的销售管理结果发送到上级终端的结果报告服务器; 并收到销售管理结果报告，并对销售管理结果发表意见的高级终端。

3. 发明申请

US20110032759A1 MEMORY SYSTEM AND RELATED METHOD OF PROGRAMMING 有权
标题翻译：记忆系统及相关编程方法
公开(公告)号：US20110032759A1
公开(公告)日：2011-02-10
申请号：US12832220
申请日：2010-07-08
申请人： Yong June Kim , Jae hong Kim , Ki Jun Lee
发明人： Yong June Kim , Jae hong Kim , Ki Jun Lee
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C7/1012 , G11C11/5642 , G11C2211/5647
摘要： A method of programming a nonvolatile memory device comprises counting a number of state pairs in a unit of input data, modulating the unit of input data to reduce the number of state pairs contained therein, and programming the modulated unit of input data in the nonvolatile memory device. Each state pair comprises data with a first state and designated for programming in a memory cell connected to a first word line, and data with a second state and designated for programming in a memory cell connected to a second word line adjacent to the first word line. The memory cell connected to the first word line is adjacent to the memory cell connected to the second word line.
摘要翻译：一种对非易失性存储器件进行编程的方法包括以输入数据为单位对多个状态对进行计数，调制输入数据的单位以减少其中包含的状态对的数量，并将输入数据的调制单元编程在非易失性存储器设备。每个状态对包括具有第一状态并被指定用于在连接到第一字线的存储器单元中进行编程的数据，以及具有第二状态并被指定用于在连接到与第一字线相邻的第二字线的存储器单元中编程的数据。连接到第一字线的存储单元与连接到第二字线的存储单元相邻。

4. 发明申请

US20090276687A1 METHOD OF ENCODING AND DECODING MULTI-BIT LEVEL DATA 有权
标题翻译：编码和解码多级数据的方法
公开(公告)号：US20090276687A1
公开(公告)日：2009-11-05
申请号：US12429718
申请日：2009-04-24
申请人： Yong June KIM , Jae Hong KIM , Kyoung Lae CHO , Jun Jin KONG , Ki Jun LEE , Ha Bong CHUNG , Keun Sung CHOI
发明人： Yong June KIM , Jae Hong KIM , Kyoung Lae CHO , Jun Jin KONG , Ki Jun LEE , Ha Bong CHUNG , Keun Sung CHOI
IPC分类号： H03M13/19 , G06F11/10 , H03M13/45
CPC分类号： H03M13/451 , G06F11/1072
摘要： A method of encoding multi-bit level data includes: determining a range of an error pattern generated according to a transmission symbol, encoding an M-bit level of a P-bit level corresponding to the transmission symbol based on the range of the error pattern, and excluding encoding of a P-M bit level of the P-bit level. The variable P is a natural number of a value at least two, and the variable M is a natural number less than P.
摘要翻译：一种编码多位电平数据的方法包括：根据传输符号确定产生的误差模式的范围，根据误差模式的范围来编码与发送符号对应的P位电平的M位电平，并且排除P位电平的PM位电平的编码。变量P是至少为2的值的自然数，变量M是小于P的自然数。

5. 发明授权

US08448048B2 Flash memory device and related programming method 有权
标题翻译：闪存设备及相关编程方法
公开(公告)号：US08448048B2
公开(公告)日：2013-05-21
申请号：US12769692
申请日：2010-04-29
申请人： Ki jun Lee , Hong Rak Son , Jun jin Kong
发明人： Ki jun Lee , Hong Rak Son , Jun jin Kong
IPC分类号： G11C29/00
CPC分类号： G11C16/26 , G06F11/1072 , G11C16/06
摘要： A nonvolatile memory device comprises a memory cell array configured to store one or more bits per memory cell, a read and write circuit configured to access the memory cell array, a control logic component configured to control the read and write circuit to sequentially execute read operations of a selected memory cell at least twice to output a read data symbol, and an error correcting unit configured to correct an error in the read data symbol based on a pattern of the read data symbol to output an error-corrected symbol.
摘要翻译：非易失性存储器件包括被配置为存储每个存储器单元的一个或多个位的存储器单元阵列，被配置为访问存储单元阵列的读取和写入电路，被配置为控制读取和写入电路以顺序执行读取操作的控制逻辑组件选择的存储单元至少两次以输出读取数据符号;以及纠错单元，被配置为基于所读取的数据符号的图案校正所读取的数据符号中的错误，以输出纠错符号。

6. 发明申请

US20120221775A1 NON-VOLATILE MEMORY DEVICE AND READ METHOD THEREOF 有权
标题翻译：非易失性存储器件及其读取方法
公开(公告)号：US20120221775A1
公开(公告)日：2012-08-30
申请号：US13407333
申请日：2012-02-28
申请人： Yong June KIM , Hong Rak SON , Jae Hong KIM , Sang Yong YOON , Ki Jun LEE , Jung Soo CHUNG , Seong Hyeog CHOI
发明人： Yong June KIM , Hong Rak SON , Jae Hong KIM , Sang Yong YOON , Ki Jun LEE , Jung Soo CHUNG , Seong Hyeog CHOI
IPC分类号： G06F12/00
CPC分类号： G06F21/00 , G06F11/1012 , G06F11/108 , G06F12/00 , G06F12/14 , G11C11/00 , G11C11/5642 , G11C16/26 , G11C16/3418
摘要： An apparatus and a method for reading from a non-volatile memory whereby soft decision data is used to determine the reliability of hard decision data. The hard decision data read from the non-volatile memory is de-randomized and the soft decision data read from the non-volatile memory is not de-randomized. Using the soft decision data, the hard decision data is decoded.
摘要翻译：一种用于从非易失性存储器读取的装置和方法，由此使用软判决数据来确定硬判决数据的可靠性。从非易失性存储器读取的硬判决数据被去随机化，并且从非易失性存储器读取的软判决数据不被去随机化。使用软判决数据，硬判决数据被解码。

7. 发明申请

US20110208897A1 METHOD AND MEMORY SYSTEM USING A PRIORI PROBABILITY INFORMATION TO READ STORED DATA 有权
标题翻译：使用先验概率信息来读取存储数据的方法和存储器系统
公开(公告)号：US20110208897A1
公开(公告)日：2011-08-25
申请号：US12985397
申请日：2011-01-06
申请人： Ki jun Lee , Hong Rak Son , Jun jin Kong
发明人： Ki jun Lee , Hong Rak Son , Jun jin Kong
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G11C11/5642 , G11C16/349
摘要： A memory system comprises a non-volatile memory device that stores user data and state information regarding the user data. In a read operation of the non-volatile memory device, a memory controller calculates a priori probabilities for the user data based on the state information, calculates a posteriori probabilities based on the a priori probabilities, and performs a soft-decision operation to determine values of the user data based on the a posteriori probabilities.
摘要翻译：存储器系统包括存储用户数据和关于用户数据的状态信息的非易失性存储器件。在非易失性存储器件的读取操作中，存储器控制器基于状态信息计算用户数据的先验概率，基于先验概率计算后验概率，并执行软判决操作以确定值基于后验概率的用户数据。

8. 发明申请

US20110125975A1 INTERLEAVING APPARATUSES AND MEMORY CONTROLLERS HAVING THE SAME 有权
标题翻译：具有相同功能的装置和存储器控制器
公开(公告)号：US20110125975A1
公开(公告)日：2011-05-26
申请号：US12944807
申请日：2010-11-12
申请人： Jaehong KIM , Hee-Seok Eun , Ki-Jun Lee , Yong-June Kim
发明人： Jaehong KIM , Hee-Seok Eun , Ki-Jun Lee , Yong-June Kim
IPC分类号： G06F12/06 , G06F5/00
CPC分类号： G06F12/0607 , G06F2212/7208
摘要： An interleaving apparatus may include a first buffer unit configured to buffer input data in units having a size of a sector to generate sector unit data, an encoding unit configured to encode the sector unit data and generate a plurality of parity codes based on the encoding, a second buffer unit configured to interleave the sector unit data and the parity codes and generate interleaving data based on the interleaving, the second buffer unit including a plurality of output buffers configured to store the interleaving data, and an output unit configured to output the interleaving data.
摘要翻译：交错装置可以包括：第一缓冲器单元，被配置为以具有扇区大小的单位缓冲输入数据以产生扇区单元数据;编码单元，被配置为对扇区单元数据进行编码，并且基于编码生成多个奇偶校验码，第二缓冲器单元，被配置为交织扇区单元数据和奇偶校验码，并且基于交织产生交织数据，第二缓冲单元包括被配置为存储交织数据的多个输出缓冲器，以及输出单元，其被配置为输出交织数据。

9. 发明申请

US20080036500A1 DUAL CONTROL ANALOG DELAY ELEMENT 失效
标题翻译：双控模拟延迟元件
公开(公告)号：US20080036500A1
公开(公告)日：2008-02-14
申请号：US11833559
申请日：2007-08-03
申请人： Ki-Jun LEE , Gurpreet BHULLAR
发明人： Ki-Jun LEE , Gurpreet BHULLAR
IPC分类号： H03K19/00
CPC分类号： H03K5/133 , H03K5/13 , H03K5/131 , H03K2005/00032
摘要： An analog delay element for delaying an input clock signal to produce an output clock signal. The analog delay element includes a delay circuit for receiving the input clock signal and for providing an intermediate clock signal in response to a first bias voltage. A current mirror amplifier generates a first current in a first current branch in response to the intermediate clock signal, and generates a second current in a second current branch in response to the first current and a second bias voltage. The second current branch has an output node for providing the output clock signal having a logic level corresponding to the delayed intermediate clock signal logic level.
摘要翻译：用于延迟输入时钟信号以产生输出时钟信号的模拟延迟元件。模拟延迟元件包括用于接收输入时钟信号并响应于第一偏置电压提供中间时钟信号的延迟电路。电流镜放大器响应于中间时钟信号在第一电流分支中产生第一电流，并响应于第一电流和第二偏置电压在第二电流分支中产生第二电流。第二电流分支具有用于提供具有与延迟的中间时钟信号逻辑电平相对应的逻辑电平的输出时钟信号的输出节点。

10. 发明授权

US6057676A Regulated DRAM cell plate and precharge voltage generator 失效
标题翻译：调节DRAM单元板和预充电电压发生器
公开(公告)号：US6057676A
公开(公告)日：2000-05-02
申请号：US99464
申请日：1998-06-18
申请人： Ki-Jun Lee , Gurpreet Bhullar , Michael B. Vladescu
发明人： Ki-Jun Lee , Gurpreet Bhullar , Michael B. Vladescu
IPC分类号： G05F3/16 , G11C11/406
CPC分类号： G11C11/4074 , G11C11/4094 , G11C7/12
摘要： A regulator circuit is provided for use with cell plate voltage generators of memory cell capacitors and precharge bit lines voltage generators in semiconductor memories. The circuit employs a current source coupled to the charging reference voltage whose output is controlled by a level detector, which receives as input a reference level signal and the cell plate voltage. When the cell plate voltage drops below the reference level, the level detector triggers the current source, thereby recovering the cell plate voltage to the reference level. The level detector can be disabled through an input.
摘要翻译：提供一种调节器电路，用于存储单元电容器的单元板电压发生器和半导体存储器中的预充电位线电压发生器。电路采用耦合到充电参考电压的电流源，其输出由电平检测器控制，电平检测器接收参考电平信号和电池板电压作为输入。当电池板电压低于参考电平时，电平检测器触发电流源，从而将电池板电压恢复到参考电平。电平检测器可通过输入禁用。

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