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1. 发明申请

US20080036500A1 DUAL CONTROL ANALOG DELAY ELEMENT 失效
标题翻译：双控模拟延迟元件
公开(公告)号：US20080036500A1
公开(公告)日：2008-02-14
申请号：US11833559
申请日：2007-08-03
申请人： Ki-Jun LEE , Gurpreet BHULLAR
发明人： Ki-Jun LEE , Gurpreet BHULLAR
IPC分类号： H03K19/00
CPC分类号： H03K5/133 , H03K5/13 , H03K5/131 , H03K2005/00032
摘要： An analog delay element for delaying an input clock signal to produce an output clock signal. The analog delay element includes a delay circuit for receiving the input clock signal and for providing an intermediate clock signal in response to a first bias voltage. A current mirror amplifier generates a first current in a first current branch in response to the intermediate clock signal, and generates a second current in a second current branch in response to the first current and a second bias voltage. The second current branch has an output node for providing the output clock signal having a logic level corresponding to the delayed intermediate clock signal logic level.
摘要翻译：用于延迟输入时钟信号以产生输出时钟信号的模拟延迟元件。模拟延迟元件包括用于接收输入时钟信号并响应于第一偏置电压提供中间时钟信号的延迟电路。电流镜放大器响应于中间时钟信号在第一电流分支中产生第一电流，并响应于第一电流和第二偏置电压在第二电流分支中产生第二电流。第二电流分支具有用于提供具有与延迟的中间时钟信号逻辑电平相对应的逻辑电平的输出时钟信号的输出节点。

2. 发明申请

US20110185267A1 ENCODING DEVICE, CONTROLLER AND SYSTEM INCLUDING THE SAME 有权
标题翻译：编码设备，控制器和系统，包括它们
公开(公告)号：US20110185267A1
公开(公告)日：2011-07-28
申请号：US13012304
申请日：2011-01-24
申请人： Ki-Jun LEE , Jun-Jin KONG , Hong-Rak SON , Hyung-June KIM , Dong-Joon SHIN , Sung-Han JUNG , Sung-Rae KIM
发明人： Ki-Jun LEE , Jun-Jin KONG , Hong-Rak SON , Hyung-June KIM , Dong-Joon SHIN , Sung-Han JUNG , Sung-Rae KIM
IPC分类号： G06F11/08 , G06F12/02
CPC分类号： H03M13/47 , H03M13/235 , H03M13/6362 , H03M13/6368 , H03M13/6375
摘要： An encoding device includes an encoder and a puncturing unit. The encoder generates parity bits based on information bits. The puncturing unit punctures the parity bits based on a puncturing pattern complying with a first criterion determining a period of the puncturing pattern and a second criterion determining positions of remaining parity bits.
摘要翻译：编码装置包括编码器和穿孔单元。编码器基于信息比特生成奇偶校验位。删截单元根据确定打孔图案的周期的第一标准的删截图案和确定剩余奇偶校验位的位置的第二准则，对奇偶校验位进行穿刺。

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