专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5332910A Semiconductor optical device with nanowhiskers 失效
标题翻译：具有纳米晶须的半导体光学器件
公开(公告)号：US5332910A
公开(公告)日：1994-07-26
申请号：US159343
申请日：1993-11-30
申请人： Keiichi Haraguchi , Kenji Hiruma , Kensuke Ogawa , Toshio Katsuyama , Ken Yamaguchi , Toshiyuki Usagawa , Masamits Yazawa , Toshiaki Masuhara , Gerard P. Morgan , Hiroshi Kakibayashi
发明人： Keiichi Haraguchi , Kenji Hiruma , Kensuke Ogawa , Toshio Katsuyama , Ken Yamaguchi , Toshiyuki Usagawa , Masamits Yazawa , Toshiaki Masuhara , Gerard P. Morgan , Hiroshi Kakibayashi
IPC分类号： G02B6/42 , H01L33/00 , H01L33/24 , H01S3/067 , H01S5/00 , H01S5/02 , H01S5/06 , H01S5/10 , H01S5/12 , H01S5/18 , H01S5/183 , H01S5/223 , H01S5/32 , H01S5/34 , H01S5/40 , H01S5/42 , H01S5/50
CPC分类号： H01L33/24 , B82Y20/00 , G02B6/4202 , H01L33/0062 , H01S5/1228 , H01S5/183 , H01S5/4031 , H01S3/06708 , H01S5/0028 , H01S5/0217 , H01S5/0608 , H01S5/1042 , H01S5/105 , H01S5/18 , H01S5/223 , H01S5/3202 , H01S5/3412 , H01S5/4006 , H01S5/4056 , H01S5/423 , H01S5/5045
摘要： A semiconductor light-emitting device includes a plurality of semiconductor rods, each of which has a pn junction. The semiconductor rods are formed on a semiconductor substrate such that the plurality of semiconductor rods are arranged at a distance substantially equal to an integer multiple of the wavelength of light emitted from the semiconductor rod. With such devices, various novel optical devices such as a micro-cavity laser of which the threshold current is extremely small and a coherent light-emitting device having no threshold value can be realized.
摘要翻译：半导体发光器件包括多个半导体棒，每个半导体棒具有pn结。半导体棒形成在半导体衬底上，使得多个半导体棒被布置成基本上等于从半导体棒发射的光的波长的整数倍的距离。利用这样的装置，可以实现各种新颖的光学装置，例如阈值电流极小的微腔激光器和不具有阈值的相干发光装置。

2. 发明申请

US20100200909A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100200909A1
公开(公告)日：2010-08-12
申请号：US12699731
申请日：2010-02-03
申请人： Yoshiyuki Kawashima , Keiichi Haraguchi
发明人： Yoshiyuki Kawashima , Keiichi Haraguchi
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/105 , H01L27/11568 , H01L27/11573 , H01L29/66833
摘要： To provide a technique capable of improving reliability of a semiconductor device having a nonvolatile memory cell by suppressing the reduction of the drive force.A memory cell is configured by a selection pMIS having a selection gate electrode including a conductive film exhibiting a p-type conductivity and a memory pMIS having a memory gate electrode including a conductive film exhibiting a p-type conductivity, and at the time of write, hot electrons are injected into a charge storage layer from the side of a semiconductor substrate 1 and at the time of erase, hot holes are injected into the charge storage layer from the memory gate electrode.
摘要翻译：提供一种能够通过抑制驱动力的降低来提高具有非易失性存储单元的半导体器件的可靠性的技术。存储单元由具有包括具有p型导电性的导电膜的选择栅电极和具有包含具有p型导电性的导电膜的存储栅极的存储器pMIS的选择pMIS配置，并且在写入时热电子从半导体衬底1的侧面注入电荷存储层中，并且在擦除时，热电荷从存储栅电极注入电荷存储层。

3. 发明申请

US20060144272A1 Process for producing water-development printing plate for relief printing 审中-公开
标题翻译：浮雕印刷用水印版印刷工艺
公开(公告)号：US20060144272A1
公开(公告)日：2006-07-06
申请号：US10546589
申请日：2004-02-17
申请人： Keiichi Haraguchi , Masahiro Yoshida
发明人： Keiichi Haraguchi , Masahiro Yoshida
IPC分类号： B41N3/00
CPC分类号： G03F7/032 , G03F7/033 , G03F7/2024
摘要： A process for producing a water-developable printing plate for use in relief printing, comprising subjecting a solid plate made of a photosensitive resin composition including at least (a) a hydrophilic resin, (b) a hydrophobic resin, (c) a photopolymerizable unsaturated compound and (d) a photopolymerization initiator to at least an exposure step with actinic light, a development step and a post-exposure step, wherein the above described post-exposure step is carried out in a low oxygen concentration environment.
摘要翻译：一种用于印刷用水性印刷版的方法，包括使至少包含（a）亲水性树脂的感光性树脂组合物的固体板，（b）疏水性树脂，（c）光聚合性不饱和树脂化合物和（d）光聚合引发剂至少具有光化光的曝光步骤，显影步骤和曝光后步骤，其中上述后曝光步骤在低氧浓度环境中进行。

4. 发明申请

US20050164442A1 Method of manufacturing a nonvolatile semiconductor memory device 有权
标题翻译：制造非易失性半导体存储器件的方法
公开(公告)号：US20050164442A1
公开(公告)日：2005-07-28
申请号：US11036023
申请日：2005-01-18
申请人： Kenji Kanamitsu , Takashi Moriyama , Naohiro Hosoda , Keiichi Haraguchi , Tetsuo Adachi
发明人： Kenji Kanamitsu , Takashi Moriyama , Naohiro Hosoda , Keiichi Haraguchi , Tetsuo Adachi
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/8238 , H01L21/8239 , H01L21/8246 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115
摘要： An AND flash memory of the type wherein a memory cell is constituted of n-type semiconductor regions (a source and a drain) formed in a p-type well of a semiconductor substrate and three gates (including a floating gate, a control gate and a selective gate) is manufactured. In the manufacture, arsenic (As) is introduced into a p-type well in the vicinity of one of side walls of the selective gate to form n-type semiconductor regions (a source and a drain). Thereafter, to cope with a drain disturb problem, the substrate is thermally treated by use of an ISSG (In-Situ Steam Generation) oxidation method so that a first gate,insulating film disposed in the vicinity of one of side walls, at which the n-type semiconductor regions have been formed, is formed thick.
摘要翻译：一种AND闪速存储器，其中存储单元由形成在半导体衬底的p型阱中的n型半导体区域（源极和漏极）构成，并且三个栅极（包括浮动栅极，控制栅极和选择栅极）。在制造中，将砷（As）引入到选择栅极的一个侧壁附近的p型阱中以形成n型半导体区域（源极和漏极）。此后，为了应对排水干扰问题，通过使用ISSG（原位蒸汽发生）氧化法对基板进行热处理，使得设置在侧壁中的一个侧壁附近的第一栅极绝缘膜，已形成n型半导体区域，形成较厚。

5. 发明申请

US20080283889A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080283889A1
公开(公告)日：2008-11-20
申请号：US12101959
申请日：2008-04-11
申请人： Keiichi HARAGUCHI , Toshikazu Matsui , Satoshi Kamei , Hisanori Ito
发明人： Keiichi HARAGUCHI , Toshikazu Matsui , Satoshi Kamei , Hisanori Ito
IPC分类号： H01L29/94 , H01L29/92
CPC分类号： H01L27/0805 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： The present invention aims to enhance the reliability of a semiconductor device having first through fourth capacitive elements. The first through fourth capacitive elements are disposed over a semiconductor substrate. A series circuit of the first and second capacitive elements and a series circuit of the third and fourth capacitive elements are coupled in parallel between first and second potentials. Lower electrodes of the first and third capacitive elements are respectively formed by a common conductor pattern and coupled to the first potential. Lower electrodes of the second and fourth capacitive elements are respectively formed by a conductor pattern of the same layer as the above conductor pattern and coupled to the second potential. Upper electrodes of the first and second capacitive elements are respectively formed by a common conductor pattern and brought to a floating potential. Upper electrodes of the third and fourth capacitive elements are respectively formed by a conductor pattern of the same layer as the above conductor pattern and brought to a floating potential, but not coupled to the upper electrodes of the first and second capacitive elements by a conductor.
摘要翻译：本发明旨在提高具有第一至第四电容元件的半导体器件的可靠性。第一至第四电容元件设置在半导体衬底上。第一和第二电容元件的串联电路和第三和第四电容元件的串联电路在第一和第二电位之间并联耦合。第一和第三电容元件的下电极分别由公共导体图案形成并耦合到第一电位。第二和第四电容元件的下电极分别由与上述导体图案相同的层的导体图案形成并耦合到第二电位。第一和第二电容元件的上电极分别由公共导体图形形成并且具有浮动电位。第三和第四电容元件的上电极分别由与上述导体图案相同的层的导体图形形成浮动电位，但不通过导体耦合到第一和第二电容元件的上电极。

6. 发明申请

US20070034935A1 Nonvolatile semiconductor memory device and a method of the same 有权
标题翻译：非易失性半导体存储器件及其方法
公开(公告)号：US20070034935A1
公开(公告)日：2007-02-15
申请号：US11583092
申请日：2006-10-19
申请人： Keiichi Haraguchi , Masataka Kato , Kenji Kanamitsu
发明人： Keiichi Haraguchi , Masataka Kato , Kenji Kanamitsu
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , G11C16/0458 , H01L27/11521 , H01L29/42328 , H01L29/7887
摘要： A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which is formed on the first insulator film and has side faces and a top face covered with a silicon oxide film (first insular film), floating gates which are formed in a side-wall form on both sides of the selector gate and which are electrically isolated from the selector gate through the silicon oxide film, a second gate insulator film formed to cover the silicon oxide film and the surface of each of the floating gates, and a control gate formed over the second gate insulator film.
摘要翻译：促进了用于存储器件的非易失性半导体的尺寸减小和其容量的增加。闪速存储器的每个存储单元设置有场效应晶体管，其具有形成在p型阱上的第一栅极绝缘膜，形成在第一绝缘膜上并具有侧面的选择栅，并且覆盖有氧化硅膜（第一岛状膜），在选择栅的两侧以侧壁形式形成并通过氧化硅膜与选择栅极电隔离的浮栅;第二栅极绝缘膜，形成为覆盖氧化硅膜和每个浮置栅极的表面，以及形成在第二栅极绝缘膜上的控制栅极。

7. 发明授权

US07126184B2 Nonvolatile semiconductor memory device and a method of the same 有权
标题翻译：非易失性半导体存储器件及其方法
公开(公告)号：US07126184B2
公开(公告)日：2006-10-24
申请号：US11147310
申请日：2005-06-08
申请人： Keiichi Haraguchi , Masataka Kato , Kenji Kanamitsu
发明人： Keiichi Haraguchi , Masataka Kato , Kenji Kanamitsu
IPC分类号： H01L29/76 , H01L29/788 , H01L21/8238
CPC分类号： H01L27/115 , G11C16/0458 , H01L27/11521 , H01L29/42328 , H01L29/7887
摘要： A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which is formed on the first insulator film and has side faces and a top face covered with a silicon oxide film (first insular film), floating gates which are formed in a side-wall form on both sides of the selector gate and which are electrically isolated from the selector gate through the silicon oxide film, a second gate insulator film formed to cover the silicon oxide film and the surface of each of the floating gates, and a control gate formed over the second gate insulator film.
摘要翻译：促进了用于存储器件的非易失性半导体的尺寸减小和其容量的增加。闪速存储器的每个存储单元设置有场效应晶体管，其具有形成在p型阱上的第一栅极绝缘膜，形成在第一绝缘膜上并具有侧面的选择栅，并且覆盖有氧化硅膜（第一岛状膜），在选择栅的两侧以侧壁形式形成并通过氧化硅膜与选择栅极电隔离的浮栅;第二栅极绝缘膜，形成为覆盖氧化硅膜和每个浮置栅极的表面，以及形成在第二栅极绝缘膜上的控制栅极。

8. 发明申请

US20060033141A1 Method of manufacturing a semiconductor device having trenches for isolation and capacitor 审中-公开
标题翻译：制造具有用于隔离和电容器的沟槽的半导体器件的方法
公开(公告)号：US20060033141A1
公开(公告)日：2006-02-16
申请号：US11248309
申请日：2005-10-13
申请人： Tsutomu Okazaki , Daisuke Okada , Yoshihiro Ikeda , Keisuke Tsukamoto , Tatsuya Fukumura , Shoji Shukuri , Keiichi Haraguchi , Koji Kishi
发明人： Tsutomu Okazaki , Daisuke Okada , Yoshihiro Ikeda , Keisuke Tsukamoto , Tatsuya Fukumura , Shoji Shukuri , Keiichi Haraguchi , Koji Kishi
IPC分类号： H01L29/94 , H01L21/383
CPC分类号： H01L27/11536 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L29/66181 , H01L29/7833
摘要： At least not less than one capacitor formation trench providing an uneven surface is formed on the surface of a capacitor formation region. Thus, the surface area of a capacitor is increased, which enables improvement of the capacitance of the capacitor is increased, which enables improvement of the capacitance of the capacitor per unit area. Further, by forming the capacitor formation trench and an element formation trench that are formed in the surface of the semiconductor substrate by the same step, it is possible to simplify the manufacturing process. Whereas, a dielectric film of the capacitor in the capacitor formation region and a high-voltage insulating film in a MISFET formation region are formed by the same step; alternatively, the dielectric of the capacitor in the capacitor formation region and a memory gate interlayer film between a polysilicon layer and a polysilicon layer in the memory cell formation region are formed by the same step.
摘要翻译：在电容器形成区域的表面上形成至少不少于一个形成凹凸表面的电容器形成沟槽。因此，电容器的表面积增大，能够提高电容器的电容量，能够提高单位面积的电容器的电容。此外，通过形成通过相同的步骤形成在半导体衬底的表面中的电容器形成沟槽和元件形成沟槽，可以简化制造工艺。而通过相同的步骤形成电容器形成区域中的电容器的电介质膜和MISFET形成区域中的高压绝缘膜; 或者，电容器形成区域中的电容器的电介质和存储单元形成区域中的多晶硅层和多晶硅层之间的存储器栅极层间膜通过相同的步骤形成。

9. 发明申请

US20050269623A1 Nonvolatile semiconductor memory device and a method of the same 有权
标题翻译：非易失性半导体存储器件及其方法
公开(公告)号：US20050269623A1
公开(公告)日：2005-12-08
申请号：US11147310
申请日：2005-06-08
申请人： Keiichi Haraguchi , Masataka Kato , Kenji Kanamitsu
发明人： Keiichi Haraguchi , Masataka Kato , Kenji Kanamitsu
IPC分类号： H01L21/8247 , G11C11/34 , G11C16/04 , H01L27/10 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , G11C16/0458 , H01L27/11521 , H01L29/42328 , H01L29/7887
摘要： A reduction in size nonvolatile semiconductors for use in a memory device and an increase in the capacity thereof are promoted. Each memory cell of a flash memory is provided with a field effect transistor having a first gate insulator film formed on a p-type well, a selector gate which is formed on the first insulator film and has side faces and a top face covered with a silicon oxide film (first insular film), floating gates which are formed in a side-wall form on both sides of the selector gate and which are electrically isolated from the selector gate through the silicon oxide film, a second gate insulator film formed to cover the silicon oxide film and the surface of each of the floating gates, and a control gate formed over the second gate insulator film.
摘要翻译：促进了用于存储器件的非易失性半导体的尺寸减小和其容量的增加。闪速存储器的每个存储单元设置有场效应晶体管，其具有形成在p型阱上的第一栅极绝缘膜，形成在第一绝缘膜上并具有侧面的选择栅，并且覆盖有氧化硅膜（第一岛状膜），在选择栅的两侧以侧壁形式形成并通过氧化硅膜与选择栅极电隔离的浮栅;第二栅极绝缘膜，形成为覆盖氧化硅膜和每个浮置栅极的表面，以及形成在第二栅极绝缘膜上的控制栅极。

10. 发明授权

US08344444B2 Semiconductor device having a nonvolatile memory cell with a cap insulating film formed over a selection gate electrode 有权
标题翻译：半导体器件具有在选择栅电极上形成的具有帽绝缘膜的非易失性存储单元
公开(公告)号：US08344444B2
公开(公告)日：2013-01-01
申请号：US12699731
申请日：2010-02-03
申请人： Yoshiyuki Kawashima , Keiichi Haraguchi
发明人： Yoshiyuki Kawashima , Keiichi Haraguchi
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/105 , H01L27/11568 , H01L27/11573 , H01L29/66833
摘要： To provide a technique capable of improving reliability of a semiconductor device having a nonvolatile memory cell by suppressing the reduction of the drive force.A memory cell is configured by a selection pMIS having a selection gate electrode including a conductive film exhibiting a p-type conductivity and a memory pMIS having a memory gate electrode including a conductive film exhibiting a p-type conductivity, and at the time of write, hot electrons are injected into a charge storage layer from the side of a semiconductor substrate 1 and at the time of erase, hot holes are injected into the charge storage layer from the memory gate electrode.
摘要翻译：提供一种能够通过抑制驱动力的降低来提高具有非易失性存储单元的半导体器件的可靠性的技术。存储单元由具有包括具有p型导电性的导电膜的选择栅电极和具有包含具有p型导电性的导电膜的存储栅极的存储器pMIS的选择pMIS配置，并且在写入时热电子从半导体衬底1的侧面注入电荷存储层中，并且在擦除时，热电荷从存储栅电极注入电荷存储层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式