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    • 2. 发明授权
    • Multiplier circuit having circuit wide dynamic range with reduced supply
voltage requirements
    • 具有电路宽动态范围的乘法电路,具有降低的电源电压要求
    • US5521544A
    • 1996-05-28
    • US325596
    • 1994-10-19
    • Kazuomi Hatanaka
    • Kazuomi Hatanaka
    • G06G7/16G06G7/24G06F7/556
    • G06G7/24
    • A multiplier circuit including a first voltage supply for supplying a first voltage; a second voltage supply for supplying a second voltage; and a control section having a first terminal through which an input current flows, a second terminal through which a current equal to or a constant multiple of the input current at the first terminal flows, the first voltage being supplied to the second terminal, a third terminal through which an output current flows, and a fourth terminal through which a current equal to or a constant multiple of the output current at the third terminal. The second voltage is applied to the fourth terminal. The control section controls the output current so that a logarithm of a ratio of an absolute value of the output current to an absolute value of the input current is in proportion to a difference between the first voltage and the second voltage.
    • 一种乘法器电路,包括用于提供第一电压的第一电压源; 用于提供第二电压的第二电压源; 以及控制部,其具有输入电流流过的第一端子,第一端子上的输入电流等于或恒定倍数的电流流过的第二端子,向第二端子供给的第一电压,第三端子 输出电流流过的端子;以及第四端子,通过所述第四端子,所述第三端子的输出电流等于或恒定倍数。 第二电压被施加到第四端子。 控制部分控制输出电流,使得输出电流的绝对值与输入电流的绝对值的比率的对数与第一电压和第二电压之间的差成比例。
    • 4. 发明授权
    • Differential amplifier circuit
    • 差分放大电路
    • US5699010A
    • 1997-12-16
    • US667708
    • 1996-06-21
    • Kazuomi Hatanaka
    • Kazuomi Hatanaka
    • H03F1/32H03F3/45
    • H03F3/45098H03F1/3211H03F2203/45561H03F2203/45584H03F2203/45612H03F2203/45702
    • At the input sides of matched first and second differential amplifiers 11 and 12, first and second input buffers 21 and 22, and third and fourth input buffers 23 and 24 are respectively connected. In input transistors Q5 and Q8 in the first and second input buffers 21 and 22, emitter currents corresponding to the collector currents of differential transistors Q3 and Q4 of the second differential amplifier 12 flow by using current mirror circuits. Changes of base-emitter voltage of the PNP transistors Q5 and Q8, and changes of base-emitter voltage of NPN transistors Q1 and Q2 cancel each other, and an output voltage improved in linearity is obtained between a negative phase output terminal 33 and a positive phase output terminal 34.
    • 在匹配的第一和第二差分放大器11和12的输入侧,分别连接有第一和第二输入缓冲器21和22以及第三和第四输入缓冲器23和24。 在第一和第二输入缓冲器21和22中的输入晶体管Q5和Q8中,与第二差分放大器12的差分晶体管Q3和Q4的集电极电流相对应的发射极电流通过使用电流镜电路流动。 PNP晶体管Q5和Q8的基极 - 发射极电压的变化以及NPN晶体管Q1和Q2的基极 - 发射极电压的变化彼此抵消,并且在负相输出端子33和正极之间获得线性改善的输出电压 相输出端子34。