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1. 发明授权

US06216018B1 Telephone hand-free apparatus 失效
标题翻译：电话免提设备
公开(公告)号：US06216018B1
公开(公告)日：2001-04-10
申请号：US09129639
申请日：1998-08-05
申请人： Yukio Nakanishi , Yasuhisa Nakahara , Yasuhiro Kobayashi , Yoshihisa Takemori , Koichiro Haga , Kohei Hashimoto , Kazuhiko Fujimoto
发明人： Yukio Nakanishi , Yasuhisa Nakahara , Yasuhiro Kobayashi , Yoshihisa Takemori , Koichiro Haga , Kohei Hashimoto , Kazuhiko Fujimoto
IPC分类号： H04B138
CPC分类号： H04M1/6041 , H04M1/6075
摘要： A telephone hand-free apparatus comprises a housing; a telephone receiving case installed in the housing, the telephone receiving case being so sized and constructed as to receive therein a portable telephone; a board on which a control circuit is arranged, the board being installed in the housing; an external microphone operatively connected to the control circuit and exposed to the outside of the housing; an external speaker operatively connected to the control circuit and installed in the housing; a connection cable extending from the control circuit, so that when the connection cable is connected to a socket of the portable telephone, the external microphone and the external speaker become operative in place of a microphone and a speaker of the portable telephone; and an electric power source which energizes the control circuit. The control circuit includes a muting section which makes the external microphone inoperative while the control circuit is receiving a voice signal from the portable telephone through the connection cable.
摘要翻译：一种电话免提装置，包括一个外壳; 安装在外壳中的电话接收盒，电话接收盒的尺寸和构造尺寸被构造成在其中容纳便携式电话; 布置有控制电路的板，所述板安装在所述壳体中; 可操作地连接到所述控制电路并暴露于所述壳体的外部的外部麦克风; 可操作地连接到所述控制电路并安装在所述壳体中的外部扬声器; 从所述控制电路延伸的连接电缆，使得当所述连接电缆连接到所述便携式电话的插座时，所述外部麦克风和所述外部扬声器可操作地代替所述便携式电话的麦克风和扬声器; 以及使控制电路通电的电源。控制电路包括使控制电路通过连接电缆从便携式电话接收语音信号时使外部麦克风不起作用的静噪部分。

2. 发明申请

US20090193374A1 METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, DESIGNING APPARATUS, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：设计半导体集成电路器件，设计器件和半导体集成电路器件的方法
公开(公告)号：US20090193374A1
公开(公告)日：2009-07-30
申请号：US12352206
申请日：2009-01-12
申请人： Kazuhiko FUJIMOTO , Kenji Yokoyama , Takeya Fujino , Takako Ohashi , Hiromasa Fukazawa , Yohei Takagi , Kazuhisa Fujita
发明人： Kazuhiko FUJIMOTO , Kenji Yokoyama , Takeya Fujino , Takako Ohashi , Hiromasa Fukazawa , Yohei Takagi , Kazuhisa Fujita
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , G06F17/5031 , H01L24/02 , H01L2924/01004 , H01L2924/10253 , H01L2924/14 , H01L2924/00
摘要： As a method for considering the adverse influence of the stresses caused form the pad, two sorts of methods are provided. As one method, while delay variation values of cells caused by an adverse influence of stresses are calculated, the calculated delay variation values are applied to the cells so as to perform a timing analysis, and the like by considering the adverse influence of the stresses. Then, in order that a flip chip type LSI is designed by employing a result of the above-described analysis in such a manner that the adverse influence of the stresses applied from the pad is not given to vias, wiring lines, and cells located under the pad, such a physical structure that no via is arranged under the pad is employed.
摘要翻译：作为考虑由衬垫引起的应力的不利影响的方法，提供了两种方法。作为一种方法，当计算由应力的不利影响引起的电池的延迟变化值时，将所计算的延迟变化值应用于电池，以便通过考虑应力的不利影响进行定时分析等。然后，为了通过采用上述分析的结果来设计倒装芯片型LSI，使得不会对由焊盘施加的应力的不利影响赋予位于下面的通孔，布线和电池采用垫，这样的物理结构，没有通孔布置在垫下方。

3. 发明授权

US07093222B2 Power supply wiring method for semiconductor integrated circuit and semiconductor integrated circuit 有权
标题翻译：半导体集成电路和半导体集成电路的电源布线方法
公开(公告)号：US07093222B2
公开(公告)日：2006-08-15
申请号：US10653940
申请日：2003-09-04
申请人： Kazuhiko Fujimoto
发明人： Kazuhiko Fujimoto
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L23/5286 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： A power supply wiring method for a semiconductor integrated circuit is disclosed in which power supply provision for logic cells can be performed without invading the wiring area, and a semiconductor integrated circuit is also disclosed. In the power supply wiring method, a power supply is fed to logic cells located between the functional blocks of a semiconductor integrated circuit comprising a plurality of functional blocks. In the method, power supply provision similar to that for logic cells in the functional blocks is performed for the logic cells between the functional blocks by aligning logic cell rows in the functional blocks and logic cell rows located between the functional blocks. Thus, power supply provision similar to a power supply feeding method for the logic cells in the functional blocks is also possible for the logic cells located between the functional blocks.
摘要翻译：公开了一种用于半导体集成电路的电源布线方法，其中可以在不侵入布线区域的情况下执行用于逻辑单元的电源供给，并且还公开了半导体集成电路。在电源布线方法中，电源被馈送到位于包括多个功能块的半导体集成电路的功能块之间的逻辑单元。在该方法中，通过对准功能块中的逻辑单元行和位于功能块之间的逻辑单元行，对功能块之间的逻辑单元执行类似于功能块中的逻辑单元的电源供应。因此，与位于功能块中的逻辑单元的电源馈送方法类似的电源提供对于位于功能块之间的逻辑单元也是可能的。

4. 发明授权

US07831949B2 Method of designing semiconductor integrated circuit, designing apparatus, semiconductor integrated circuit system, semiconductor integrated circuit mounting substrate, package and semiconductor integrated circuit 有权
标题翻译：半导体集成电路设计方法，设计装置，半导体集成电路系统，半导体集成电路安装基板，封装和半导体集成电路
公开(公告)号：US07831949B2
公开(公告)日：2010-11-09
申请号：US11819573
申请日：2007-06-28
申请人： Shinya Tokunaga , Mitsumi Ito , Nobufusa Iwanishi , Koichi Seko , Hiroaki Suzuki , Hiroyuki Tanaka , Yuichi Nishimura , Kazuhiko Fujimoto
发明人： Shinya Tokunaga , Mitsumi Ito , Nobufusa Iwanishi , Koichi Seko , Hiroaki Suzuki , Hiroyuki Tanaka , Yuichi Nishimura , Kazuhiko Fujimoto
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L23/49838 , H01L23/50 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/49112 , H01L2224/49171 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01056 , H01L2924/01057 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/01087 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： To provide a method of designing a semiconductor integrated circuit with a high workability also in an increase in a scale of an LSI and an enhancement in an integration and designing a semiconductor integrated circuit system in which an unnecessary radiation is reduced and which is excellent in a heat characteristic, a reverse design flow to that in the conventional art is implemented, and a mounting substrate such as a printed-circuit board is first designed and a package substrate for mounting an LSI is designed based on a result of the design of the mounting substrate, and a layout design of the LSI to be mounted on the package substrate is then carried out.
摘要翻译：为了提供一种设计具有高可加工性的半导体集成电路的方法，同时也增加了LSI的规模，并提高了集成度，并设计了一种半导体集成电路系统，其中不必要的辐射被减少，并且在热特性，实现了与传统技术相反的设计流程，并且首先设计诸如印刷电路板的安装基板，并且基于安装的设计结果设计用于安装LSI的封装基板然后执行基板和要安装在封装基板上的LSI的布局设计。

5. 发明授权

US6128987A Hydraulic press for forming metal plates 失效
标题翻译：液压机用于成型金属板
公开(公告)号：US6128987A
公开(公告)日：2000-10-10
申请号：US026329
申请日：1998-02-19
申请人： Tatsuji Nakagawa , Itaru Fujimura , Hiroshi Hosoya , Junkichi Comikawa , Kazuhiko Fujimoto
发明人： Tatsuji Nakagawa , Itaru Fujimura , Hiroshi Hosoya , Junkichi Comikawa , Kazuhiko Fujimoto
IPC分类号： B30B1/32 , B30B15/16 , B30B15/24 , B26D5/20 , B21D31/02 , B30B1/42
CPC分类号： B30B1/323 , B30B15/161 , B30B15/24 , Y10T83/18 , Y10T83/4473
摘要： A hydraulic press has closed loop feedback control on a slide, a slide pad and bolster cylinders. Hydraulic cylinders actuating various components of the press are controlled according to ideal position estimates to produce consistent and precise pressing action. A closed loop control consists of an ideal position/pressure value generator, a position/pressure detector and an arithmetic unit comparing the ideal and actual position/pressure values. Using the ideal and actual comparison result, the arithmetic unit produces a control signal to drive a cylinder to a desired position/pressure. The hydraulic press is capable of performing several operations on a workpiece in one press cycle, an improvement over presses requiring several operation steps or die changes. The bolster cylinders augment clamping force, reduce shock, and improve die alignment to produce better results with less wear on press components.
摘要翻译：液压机在滑块，滑垫和缓冲气缸上具有闭环反馈控制。根据理想的位置估计来控制致动压力机各部件的液压缸，以产生一致和精确的按压作用。闭环控制包括理想的位置/压力值发生器，位置/压力检测器和运算单元，比较理想位置/压力值。使用理想和实际的比较结果，算术单元产生控制信号以将气缸驱动到期望的位置/压力。液压机能够在一个冲压循环中对工件进行多次操作，对需要几个操作步骤或模具更换的冲压进行改进。垫圈缸增加夹紧力，减少冲击，并改善模具对准以产生更好的结果，同时减少冲压部件的磨损。

6. 发明申请

US20080197449A1 WIRING STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND METHOD AND DEVICE FOR DESIGNING THE SAME 审中-公开
标题翻译：半导体集成电路装置的布线结构及其设计方法和装置
公开(公告)号：US20080197449A1
公开(公告)日：2008-08-21
申请号：US12035230
申请日：2008-02-21
申请人： Takayuki ARAKI , Junichi Shimada , Hirokazu Ogawa , Kazuhiko Fujimoto , Tsutomu Fujii , Takuya Yasui
发明人： Takayuki ARAKI , Junichi Shimada , Hirokazu Ogawa , Kazuhiko Fujimoto , Tsutomu Fujii , Takuya Yasui
IPC分类号： H01L23/52
CPC分类号： H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for designing a wiring structure of a wiring layer of a semiconductor integrated circuit device. The method includes a wire width detecting step of detecting a wire width of each wire in a wiring pattern of layout data, a wire identifying step of identifying a wire having a predetermined wire width or more based on a result of detection by the wire width detecting step, a wiring pitch detecting step of detecting a wiring pitch between the wire identified by the wire identifying step and another wire, and an air gap-forbidden region forming and removing step of forming or removing an air gap-forbidden region, depending on a result of detection by the wiring pitch detecting step.
摘要翻译：提供一种用于设计半导体集成电路器件的布线层的布线结构的方法。该方法包括：线宽检测步骤，检测布线数据的布线图案中的每条线的线宽;线识别步骤，基于线宽检测的检测结果识别具有预定线宽或更大的线的线; 步骤，检测由线识别步骤识别的线与另一线之间的布线间距的接线间距检测步骤以及形成或除去气隙禁止区域的气隙禁止区形成和移除步骤，通过布线间距检测步骤的检测结果。

7. 发明授权

US06764243B1 Split boots and method of connecting the boots, depositing agent, and heating body 有权
标题翻译：分开靴子和连接靴子，沉积剂和加热体的方法
公开(公告)号：US06764243B1
公开(公告)日：2004-07-20
申请号：US09700715
申请日：2000-11-27
申请人： Yasuaki Inuzuka , Yoshifumi Kojima , Hiromitsu Yamoto , Yukihisa Tateishi , Kenichi Fujimoto , Kazuhiko Fujimoto , Atsushi Nagashima
发明人： Yasuaki Inuzuka , Yoshifumi Kojima , Hiromitsu Yamoto , Yukihisa Tateishi , Kenichi Fujimoto , Kazuhiko Fujimoto , Atsushi Nagashima
IPC分类号： F16J304
CPC分类号： F16J3/045 , Y10T403/31 , Y10T403/32729 , Y10T403/477
摘要： A protruding part formed on one split end part of a boot is temporarily fixed to a recessed part formed on the other split end part in the state where step-shaped hook portions formed on one-end thereof are engagingly locked to each other, and connected by welding, fusion or adhesion. The protruding part is hooked only in one thickness directional side. An overlapping protruding part formed on the non-hook side (inner side) of the recessed part is connected extending over the inside surface of the protruding part and the inside surface of the split end part continued thereto.
摘要翻译：形成在靴子的一个分割端部上的突出部临时固定在形成在另一分割端部的凹部，其中形成在其一端的台阶状钩部彼此卡合，并且连接通过焊接，熔接或粘合。突出部分仅在一个厚度方向侧上钩挂。形成在凹部的非钩侧（内侧）上的重叠突出部分连接在突出部分的内表面和与其分开的分割端部的内表面上。

8. 发明授权

US08487423B2 Interconnect structure of semiconductor integrated circuit and semiconductor device including the same 有权
标题翻译：半导体集成电路的互连结构和包括其的半导体器件
公开(公告)号：US08487423B2
公开(公告)日：2013-07-16
申请号：US13169398
申请日：2011-06-27
申请人： Yoichi Matsumura , Chie Kabuo , Takako Ohashi , Tadafumi Kadota , Kazuhiko Fujimoto , Hirofumi Miyashita
发明人： Yoichi Matsumura , Chie Kabuo , Takako Ohashi , Tadafumi Kadota , Kazuhiko Fujimoto , Hirofumi Miyashita
IPC分类号： H01L23/52
CPC分类号： H01L23/5286 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor integrated circuit chip including an interconnect layer in which there is a limitation on the lengths of interconnects or areas occupied by the interconnects, empty spaces between power supply interconnect segments having the same potential located in parallel to a priority interconnect direction, are shifted relative to each other within the limits of the lengths and areas of power supply interconnects. As a result, a local increase in resistance is dispersed, whereby an influence on a voltage drop is reduced.
摘要翻译：在具有互连层的互连层的互连层的半导体集成电路芯片中，互连的占用面积的区域有限制，具有与优先级互连方向平行的相同电位的电源互连区段之间的空位被移位在电源互连的长度和面积的限度内相对于彼此。结果，电阻的局部增加被分散，从而降低对电压降的影响。

9. 发明申请

US20110260333A1 INTERCONNECT STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权
标题翻译：半导体集成电路和包括其中的半导体器件的互连结构
公开(公告)号：US20110260333A1
公开(公告)日：2011-10-27
申请号：US13169398
申请日：2011-06-27
申请人： Yoichi MATSUMURA , Chie Kabuo , Takako Ohashi , Tadafumi Kadota , Kazuhiko Fujimoto , Hirofumi Miyashita
发明人： Yoichi MATSUMURA , Chie Kabuo , Takako Ohashi , Tadafumi Kadota , Kazuhiko Fujimoto , Hirofumi Miyashita
IPC分类号： H01L23/48
CPC分类号： H01L23/5286 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor integrated circuit chip including an interconnect layer in which there is a limitation on the lengths of interconnects or areas occupied by the interconnects, empty spaces between power supply interconnect segments having the same potential located in parallel to a priority interconnect direction, are shifted relative to each other within the limits of the lengths and areas of power supply interconnects. As a result, a local increase in resistance is dispersed, whereby an influence on a voltage drop is reduced.
摘要翻译：在具有互连层的互连层的互连层的半导体集成电路芯片中，互连的占用面积的区域有限制，具有与优先级互连方向平行的相同电位的电源互连区段之间的空位被移位在电源互连的长度和面积的限度内相对于彼此。结果，电阻的局部增加被分散，从而降低对电压降的影响。

10. 发明申请

US20110012260A1 METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGNING APPARATUS, SEMICONDUCTOR INTEGRATED CIRCUIT SYSTEM, SEMICONDUCTOR INTEGRATED CIRCUIT MOUNTING SUBSTRATE, PACKAGE AND SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：设计半导体集成电路的方法，设计器件，半导体集成电路系统，半导体集成电路安装基板，封装和半导体集成电路
公开(公告)号：US20110012260A1
公开(公告)日：2011-01-20
申请号：US12892273
申请日：2010-09-28
申请人： Shinya TOKUNAGA , Mitsumi Ito , Nobufusa Iwanishi , Koichi Seko , Hiroaki Suzuki , Hiroyuki Tanaka , Yuichi Nishimura , Kazuhiko Fujimoto
发明人： Shinya TOKUNAGA , Mitsumi Ito , Nobufusa Iwanishi , Koichi Seko , Hiroaki Suzuki , Hiroyuki Tanaka , Yuichi Nishimura , Kazuhiko Fujimoto
IPC分类号： H01L23/485 , G06F17/50
CPC分类号： G06F17/5068 , H01L23/49838 , H01L23/50 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/49112 , H01L2224/49171 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01056 , H01L2924/01057 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/01087 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： To provide a method of designing a semiconductor integrated circuit with a high workability also in an increase in a scale of an LSI and an enhancement in an integration and designing a semiconductor integrated circuit system in which an unnecessary radiation is reduced and which is excellent in a heat characteristic, a reverse design flow to that in the conventional art is implemented, and a mounting substrate such as a printed-circuit board is first designed and a package substrate for mounting an LSI is designed based on a result of the design of the mounting substrate, and a layout design of the LSI to be mounted on the package substrate is then carried out.
摘要翻译：为了提供一种设计具有高可加工性的半导体集成电路的方法，同时也增加了LSI的规模，并提高了集成度，并设计了一种半导体集成电路系统，其中不必要的辐射被减少，并且在热特性，实现了与传统技术相反的设计流程，并且首先设计诸如印刷电路板的安装基板，并且基于安装的设计结果设计用于安装LSI的封装基板然后执行基板和要安装在封装基板上的LSI的布局设计。

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