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1. 发明申请

US20200303176A1 METHOD AND DEVICE FOR PREPARING MEASUREMENT SAMPLE FOR MALDI MASS SPECTROMETRY, MEASUREMENT SAMPLE FOR MALDI MASS SPECTROMETRY, MALDI MASS SPECTROMETRY METHOD, AND NON-TRANSITORY RECORDING MEDIUM FOR PREPARING MEASUREMENT SAMPLE FOR MALDI MASS SPECTROMETRY 审中-公开
公开(公告)号：US20200303176A1
公开(公告)日：2020-09-24
申请号：US16801424
申请日：2020-02-26
申请人： Katsuyuki UEMATSU , KAZUMI SUZUKI
发明人： Katsuyuki UEMATSU , KAZUMI SUZUKI
IPC分类号： H01J49/04 , H01J49/16
摘要： A method for preparing a measurement sample for MALDI mass spectrometry, the method including applying a laser beam to a base containing a matrix disposed on a surface of the base, in a manner that the laser beam is applied to a surface of the base opposite to the surface on which the matrix is disposed, to make the matrix fly from the base to be disposed at a predetermined position of an analyte of MALDI mass spectrometry.

2. 发明授权

US07119657B2 Polysilicon resistor semiconductor device 有权
标题翻译：多晶硅电阻半导体器件
公开(公告)号：US07119657B2
公开(公告)日：2006-10-10
申请号：US10120211
申请日：2002-04-10
申请人： Katsumichi Ueyanagi , Mutsuo Nishikawa , Katsuyuki Uematsu
发明人： Katsumichi Ueyanagi , Mutsuo Nishikawa , Katsuyuki Uematsu
IPC分类号： H01C1/012 , H01C7/06
CPC分类号： H01L28/20 , H01L23/522 , H01L27/0802 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a polysilicon resistor that can suppress variations in resistance value in environments with an ambient temperature higher than room temperature. The resistance value Rcon of a polysilicon contact is reduced to 2% or less of the sum of the resistance value Rcon of the polysilicon contact and the resistance value Rpoly of a polysilicon resistor. Hence, a semiconductor device that is not significantly affected by a variation in the resistance of the polysilicon contact is realized. This device suppresses variations in resistance value in environments with an ambient temperature higher than room temperature.
摘要翻译：半导体器件包括可以抑制环境温度高于室温的环境中的电阻值变化的多晶硅电阻器。多晶硅接触的电阻值R SUB降低到多晶硅接触的电阻值R OUT的总和的2％以下，电阻值R _{多晶硅电阻器的多晶硅。因此，实现了不受多晶硅接触电阻变化的显着影响的半导体器件。该装置抑制环境温度高于室温的环境中的电阻值的变化。}

3. 发明授权

US06680512B2 Semiconductor device having an integral protection circuit 有权
标题翻译：具有整体保护电路的半导体装置
公开(公告)号：US06680512B2
公开(公告)日：2004-01-20
申请号：US10121447
申请日：2002-04-12
申请人： Mutsuo Nishikawa , Katsumichi Ueyanagi , Katsuyuki Uematsu
发明人： Mutsuo Nishikawa , Katsumichi Ueyanagi , Katsuyuki Uematsu
IPC分类号： H01L2362
CPC分类号： H01L23/5286 , H01L24/05 , H01L27/0251 , H01L2224/05553 , H01L2924/12035 , H01L2924/12036 , H01L2924/12043 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要： A CMOS device with an integral reverse connection protection circuit having a low impedance region, whose impedance becomes lowest when a Vcc pad to which is to be supplied power supply voltage and a GND pad to which is to be supplied ground potential are connected in reverse polarity. The low impedance region, Vcc pad and GND pad are electrically connected through a metal line and a metal line, and current is diverted into the low impedance region during the reverse connection so as to protect an internal circuit. Surge protection elements with identical characteristics are disposed in proximity to three sides or four sides of a pad, and each side of the pad and the surge protection element corresponding thereto are electrically connected to each other, so that surge current applied to the pad is dispersed to the plurality of surge protection elements to protect the internal circuit.
摘要翻译：具有整体反向连接保护电路的CMOS器件，其具有低阻抗区域，当要提供电源电压的Vcc焊盘和要被提供接地电位的GND焊盘的阻抗变为最低时，反相极性连接。低阻抗区域Vcc焊盘和GND焊盘通过金属线和金属线电连接，并且在反向连接期间电流被转移到低阻抗区域中，以保护内部电路。具有相同特性的浪涌保护元件设置在焊盘的三边或四边附近，焊盘和对应于其的浪涌保护元件的每一侧彼此电连接，使得施加到焊盘的浪涌电流被分散到多个浪涌保护元件以保护内部电路。

4. 发明授权

US08237505B2 Signal amplification circuit 有权
标题翻译：信号放大电路
公开(公告)号：US08237505B2
公开(公告)日：2012-08-07
申请号：US12588123
申请日：2009-10-05
申请人： Mutsuo Nishikawa , Katsuyuki Uematsu , Kazuhiro Matsunami
发明人： Mutsuo Nishikawa , Katsuyuki Uematsu , Kazuhiro Matsunami
IPC分类号： H03F1/08 , H03F3/45
CPC分类号： H03F3/45179 , H03F3/45085 , H03F3/45475 , H03F3/45659 , H03F2200/261 , H03F2203/45418 , H03F2203/45424 , H03F2203/45646
摘要： This invention provides a low-current consumption type signal amplification circuit, which limits the output voltage to fix a lower-limit (upper-limit) saturation voltage of the amplification circuit at a predetermined lower-limit (upper-limit) limiting voltage. The signal amplification circuit comprises a negative feedback amplification circuit, a lower-limit voltage limiting circuit and an upper-limit voltage limiting circuit. The lower-limit voltage limiting circuit increases a resistance between an output terminal of the negative feedback amplification circuit and a ground terminal when the output voltage of the negative feedback amplification circuit falls below the lower-limit limiting voltage. The upper-limit voltage limiting circuit increases a resistance between the output terminal of the negative feedback amplification circuit and a high-potential side of a power supply when the output voltage of the negative feedback amplification circuit rises above the upper-limit limiting voltage.
摘要翻译：本发明提供了一种低电流消耗型信号放大电路，其限制输出电压，将放大电路的下限（上限）饱和电压固定在预定的下限（上限）限制电压。信号放大电路包括负反馈放大电路，下限电压限制电路和上限电压限制电路。当负反馈放大电路的输出电压低于下限极限电压时，下限电压限制电路增加负反馈放大电路的输出端子与接地端子之间的电阻。当负反馈放大电路的输出电压超过上限极限电压时，上限电压限制电路增加负反馈放大电路的输出端子与电源的高电位侧之间的电阻。

5. 发明授权

US07772658B2 Semiconductor device and method of manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07772658B2
公开(公告)日：2010-08-10
申请号：US11849328
申请日：2007-09-03
申请人： Katsuyuki Uematsu , Shigeru Shinoda , Kimihiro Ashino
发明人： Katsuyuki Uematsu , Shigeru Shinoda , Kimihiro Ashino
IPC分类号： H01L29/84
CPC分类号： H01R43/24 , G01L19/0084 , H01L23/057 , H01L2224/05554 , H01L2224/48091 , H01L2224/49171 , H01L2224/49175 , H01L2924/01079 , H01R13/405 , H01R13/6683 , H05K3/202 , H01L2924/00014
摘要： A lead frame which is disposed in an outer package is composed of three members. The lead frame is provided with contact electrodes, connector terminals, and conductive interconnections which are connected to the respective connector terminals. The arrangement order of the contact electrodes is such that contact electrodes are connected to the connector terminals, respectively; that is, the arrangement direction of the contact electrodes is the same as that of the connector terminals. On the other hand, the arrangement order of the contact electrodes is such that contact electrodes are connected to the connector terminals, respectively, that is, the arrangement direction of the contact electrodes is opposite to that of the connector terminals. Lead terminals of a resin cell package are connected to the contact electrodes.
摘要翻译：设置在外包装中的引线框架由三个构件组成。引线框架设置有连接到各个连接器端子的接触电极，连接器端子和导电互连。接触电极的排列顺序是这样的，接触电极分别连接到连接器端子; 也就是说，接触电极的布置方向与连接器端子的排列方向相同。另一方面，接触电极的排列顺序使得接触电极分别连接到连接器端子，即接触电极的布置方向与连接器端子的布置方向相反。树脂电池组的引线端子与接触电极连接。

6. 发明授权

US06684371B2 Layout of semiconductor integrated circuit 有权
标题翻译：半导体集成电路布局
公开(公告)号：US06684371B2
公开(公告)日：2004-01-27
申请号：US10117340
申请日：2002-04-08
申请人： Katsuyuki Uematsu , Mutsuo Nishikawa , Katsumichi Ueyanagi
发明人： Katsuyuki Uematsu , Mutsuo Nishikawa , Katsumichi Ueyanagi
IPC分类号： G06F1750
CPC分类号： G06F17/5068 , H01L2224/05553
摘要： To improve the capability to withstand noises and surges in a semiconductor integrated circuit in which an RC filter for cutting electromagnetic wave noises is integrated with analog circuits and digital circuits, a positive electrode of a capacitor constituting the RC filter is disposed apart from circuit elements or connection lines constituting the circuits at such an interval as to prevent malfunction of the circuit elements resulting from a noise superimposed on the positive electrode, or dielectric breakdown of the capacitor constituting the RC filter and latch-up and dielectric breakdown of the circuit elements resulting from a surge applied to the positive electrode. The interval is larger than the minimum interval required by a layout rule or five times longer than the minimum.
摘要翻译：为了提高在用于切割电磁波噪声的RC滤波器与模拟电路和数字电路集成的半导体集成电路中抵抗噪声和浪涌的能力，构成RC滤波器的电容器的正电极与电路元件或构成电路的连接线以这样的间隔来防止由叠加在正电极上的噪声导致的电路元件的故障，或者构成RC滤波器的电容器的电介质击穿以及由此产生的电路元件的闭锁和电介质击穿施加到正电极的浪涌。间隔大于布局规则所需的最小间隔或比最小值长五倍的间隔。

7. 发明申请

US20080054384A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080054384A1
公开(公告)日：2008-03-06
申请号：US11849328
申请日：2007-09-03
申请人： Katsuyuki UEMATSU , Shigeru SHINODA , Kimihiro ASHINO
发明人： Katsuyuki UEMATSU , Shigeru SHINODA , Kimihiro ASHINO
IPC分类号： H01L29/84 , H01L21/60 , H01L23/495
CPC分类号： H01R43/24 , G01L19/0084 , H01L23/057 , H01L2224/05554 , H01L2224/48091 , H01L2224/49171 , H01L2224/49175 , H01L2924/01079 , H01R13/405 , H01R13/6683 , H05K3/202 , H01L2924/00014
摘要： A lead frame which is disposed in an outer package is composed of three members. The lead frame is provided with contact electrodes, connector terminals, and conductive interconnections which are connected to the respective connector terminals. The arrangement order of the contact electrodes is such that contact electrodes are connected to the connector terminals, respectively; that is, the arrangement direction of the contact electrodes is the same as that of the connector terminals. On the other hand, the arrangement order of the contact electrodes is such that contact electrodes are connected to the connector terminals, respectively, that is, the arrangement direction of the contact electrodes is opposite to that of the connector terminals. Lead terminals of a resin cell package are connected to the contact electrodes.
摘要翻译：设置在外包装中的引线框架由三个构件组成。引线框架设置有连接到各个连接器端子的接触电极，连接器端子和导电互连。接触电极的排列顺序是这样的，接触电极分别连接到连接器端子; 也就是说，接触电极的布置方向与连接器端子的排列方向相同。另一方面，接触电极的排列顺序使得接触电极分别连接到连接器端子，即接触电极的布置方向与连接器端子的布置方向相反。树脂电池组的引线端子与接触电极连接。

8. 发明申请

US20060244101A1 SEMICONDUCTOR APPARATUS AND PHYSICAL QUANTITY SENSING APPARATUS 审中-公开
标题翻译：半导体装置和物理量传感装置
公开(公告)号：US20060244101A1
公开(公告)日：2006-11-02
申请号：US11278429
申请日：2006-04-03
申请人： Katsuyuki Uematsu , Katsumichi Ueyanagi
发明人： Katsuyuki Uematsu , Katsumichi Ueyanagi
IPC分类号： H01L29/00
CPC分类号： G01D3/032 , G01L9/06 , G01L19/0084 , G01L19/069 , G01L19/141
摘要： In a semiconductor device, in particular a physical quantity sensing apparatus, the length and the width of the wiring connecting a sensor internal circuit and an output or power supply pad are adjusted so that the total parasitic resistance components R1 parasitic on the wiring and the sum Rf of the resistance values of resistors in the filter circuit for countermeasuring against electromagnetic noises satisfy the relational expression R1/Rf×100
摘要翻译：在半导体装置中，特别是物理量感测装置中，调整连接传感器内部电路和输出或电源焊盘的布线的长度和宽度，使得寄生在布线上的总寄生电阻分量R1和总和用于对抗电磁噪声的滤波电路中的电阻的电阻值的Rf满足关系式R 1 / Rf×100 <25。此外，调整输出或电源焊盘与电容器之间的布线的长度和宽度以及电容器和接地焊盘之间的布线的长度和宽度，使得阻抗Za导致通过寄生电阻分量Ra和输出或电源焊盘与电容器之间的布线的电感分量La，由寄生电阻分量Rk引起的阻抗Zk和电容器之间的布线的电感分量Lk s）和接地焊盘，并且由电容器的电容分量引起的阻抗Zc总是满足要切断的电磁噪声的频率范围内的关系式Za + Zk

9. 发明申请

US20100109647A1 PHYSICAL QUANTITY SENSING APPARATUS HAVING AN INTERNAL CIRCUIT, A FILTER CIRCUIT HAVING RESISTORS, POWER SUPPLY, GROUNDING, AND OUTPUT PADS, WITH THE LENGTH AND WIDTH OF WIRING BETWEEN THE OUTPUT OR POWER SUPPLY PAD AND THE INTERNAL CIRCUIT SET SO THAT THE RESISTANCE OF RESISTORS AND THE PARASITIC RESISTANCE COMPONENT OF THE WIRING SATISFY A CERTAIN RELATIONAL EXPRESSION 审中-公开
标题翻译：具有内部电路的物理量感测装置，具有电阻，电源，接地和输出垫的滤波电路，输出或电源线与内部电路之间的接线长度和宽度设置为电阻和电阻接线对抗电阻组件满足一定的关系表达
公开(公告)号：US20100109647A1
公开(公告)日：2010-05-06
申请号：US12687392
申请日：2010-01-14
申请人： Katsuyuki UEMATSU , Katsumichi UEYANAGI
发明人： Katsuyuki UEMATSU , Katsumichi UEYANAGI
IPC分类号： G01R19/00
CPC分类号： G01D3/032 , G01L9/06 , G01L19/0084 , G01L19/069 , G01L19/141
摘要： In a semiconductor device, in particular a physical quantity sensing apparatus, the length and the width of the wiring connecting a sensor internal circuit and an output or power supply pad are adjusted so that the total parasitic resistance components R1 parasitic on the wiring and the sum Rf of the resistance values of resistors in the filter circuit for countermeasuring against electromagnetic noises satisfy the relational expression R1/Rf×100
摘要翻译：在半导体装置中，特别是物理量感测装置中，调整连接传感器内部电路和输出或电源焊盘的布线的长度和宽度，使得寄生在布线上的总寄生电阻分量R1和总和用于对抗电磁噪声的滤波电路中的电阻的电阻值的Rf满足关系式R1 / Rf×100 <25。此外，调整输出或电源焊盘与电容器之间的布线的长度和宽度以及电容器和接地焊盘之间的布线的长度和宽度，使得阻抗Za导致通过寄生电阻分量Ra和输出或电源焊盘与电容器之间的布线的电感分量La，由寄生电阻分量Rk引起的阻抗Zk和电容器之间的布线的电感分量Lk s）和接地焊盘，并且由电容器的电容分量引起的阻抗Zc总是满足要切断的电磁噪声的频率范围内的关系式Za + Zk

10. 发明申请

US20100097146A1 Signal amplification circuit 有权
标题翻译：信号放大电路
公开(公告)号：US20100097146A1
公开(公告)日：2010-04-22
申请号：US12588123
申请日：2009-10-05
申请人： Mutsuo Nishikawa , Katsuyuki Uematsu , Kazuhiro Watsunami
发明人： Mutsuo Nishikawa , Katsuyuki Uematsu , Kazuhiro Watsunami
IPC分类号： H03F1/34
CPC分类号： H03F3/45179 , H03F3/45085 , H03F3/45475 , H03F3/45659 , H03F2200/261 , H03F2203/45418 , H03F2203/45424 , H03F2203/45646
摘要： This invention provides a low-current consumption type signal amplification circuit, which limits the output voltage to fix a lower-limit (upper-limit) saturation voltage of the amplification circuit at a predetermined lower-limit (upper-limit) limiting voltage. The signal amplification circuit comprises a negative feedback amplification circuit, a lower-limit voltage limiting circuit and an upper-limit voltage limiting circuit. The lower-limit voltage limiting circuit increases a resistance between an output terminal of the negative feedback amplification circuit and a ground terminal when the output voltage of the negative feedback amplification circuit falls below the lower-limit limiting voltage. The upper-limit voltage limiting circuit increases a resistance between the output terminal of the negative feedback amplification circuit and a high-potential side of a power supply when the output voltage of the negative feedback amplification circuit rises above the upper-limit limiting voltage.
摘要翻译：本发明提供了一种低电流消耗型信号放大电路，其限制输出电压，将放大电路的下限（上限）饱和电压固定在预定的下限（上限）限制电压。信号放大电路包括负反馈放大电路，下限电压限制电路和上限电压限制电路。当负反馈放大电路的输出电压低于下限极限电压时，下限电压限制电路增加负反馈放大电路的输出端子与接地端子之间的电阻。当负反馈放大电路的输出电压超过上限极限电压时，上限电压限制电路增加负反馈放大电路的输出端子与电源的高电位侧之间的电阻。

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