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1. 发明授权

US07301237B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07301237B2
公开(公告)日：2007-11-27
申请号：US11229550
申请日：2005-09-20
申请人： Katsuhiro Uesugi , Katsuo Katayama , Katsuhisa Sakai
发明人： Katsuhiro Uesugi , Katsuo Katayama , Katsuhisa Sakai
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L21/76802 , H01L21/76829 , H01L21/76834
摘要： An etching stopper film is formed on an interlayer insulating film. A conductive layer is formed on the etching stopper film. An etching stopper film is formed to cover the conductive layer. An interlayer insulating film is formed on the etching stopper film. In a structure above, initially, a hole vertically penetrating the interlayer insulating film for exposing a surface of the etching stopper film is formed under a first etching condition. Thereafter, the etching stopper film serving as a bottom surface of the hole is removed under a second etching condition, thereby forming the hole reaching the conductive layer. An interconnection is embedded in the hole. A semiconductor device in which a hole reaching the conductive layer is prevented from extending as far as the lower interlayer insulating film as a result of misalignment, as well as a manufacturing method thereof are thus obtained.
摘要翻译：在层间绝缘膜上形成蚀刻停止膜。在蚀刻停止膜上形成导电层。形成蚀刻停止膜以覆盖导电层。在蚀刻停止膜上形成层间绝缘膜。在上述结构中，首先在第一蚀刻条件下形成垂直贯穿层间绝缘膜的用于暴露蚀刻阻挡膜的表面的孔。此后，在第二蚀刻条件下去除用作孔底的蚀刻阻挡膜，从而形成到达导电层的孔。孔中嵌有互连。由此，能够防止到达导电层的空穴的延伸到作为未对准的下层间绝缘膜的半导体装置及其制造方法。

2. 发明授权

US5951887A Plasma processing apparatus and plasma processing method 失效
标题翻译：等离子体处理装置和等离子体处理方法
公开(公告)号：US5951887A
公开(公告)日：1999-09-14
申请号：US952782
申请日：1997-11-26
申请人： Hiroshi Mabuchi , Toshihiro Hayami , Hideo Ida , Tomomi Murakami , Naohiko Takeda , Junya Tsuyuguchi , Katsuo Katayama
发明人： Hiroshi Mabuchi , Toshihiro Hayami , Hideo Ida , Tomomi Murakami , Naohiko Takeda , Junya Tsuyuguchi , Katsuo Katayama
IPC分类号： B05D7/24 , C23C16/44 , C23C16/511 , H01J37/32 , B23K10/00
CPC分类号： B05D1/62 , C23C16/4401 , C23C16/511 , H01J37/32192 , H01J37/32238 , H01J2237/022
摘要： A plasma processing apparatus and plasma processing method are provided to be used for etching, ashing, CVD, etc. in the manufacturing, etc. of large-scale integrated circuits (LSIs) and liquid crystal display panels (LCDs). The plasma processing apparatus generates plasma by using a microwave introduced through a microwave window, while controlling the ions in the plasma by varying the RF voltage applied to the sample stage. The apparatus is characterized to include a counter electrode (grounded electrode) which is located at the rim section of the microwave window against the sample stage. The plasma processing method implements a plasma process for a sample with the plasma processing apparatus. The method and apparatus are capable of alleviating the sticking of particles to the sample and metallic contamination, and also capable of improving the yield of semiconductor devices, etc.
摘要翻译： PCT No.PCT / JP97 / 01070 Sec。 371日期：1997年11月26日 102（e）日期1997年11月26日PCT 1997年3月27日PCT公布。公开号WO97 / 36461 日期1997年10月2日提供了一种等离子体处理装置和等离子体处理方法，用于大规模集成电路（LSI）和液晶显示面板（LCD）的制造等中的蚀刻，灰化，CVD等。。等离子体处理装置通过使用通过微波窗口引入的微波产生等离子体，同时通过改变施加到样品台的RF电压来控制等离子体中的离子。该装置的特征在于包括相对电极（接地电极），其位于微波窗口的边缘部分处抵靠样品台。等离子体处理方法利用等离子体处理装置对样品进行等离子体处理。该方法和装置能够减轻颗粒对样品的粘附和金属污染，并且还能够提高半导体器件的产量等。

3. 发明授权

US5545258A Microwave plasma processing system 失效
标题翻译：微波等离子体处理系统
公开(公告)号：US5545258A
公开(公告)日：1996-08-13
申请号：US490088
申请日：1995-06-13
申请人： Katsuo Katayama , Kyoichi Komachi , Hiroshi Mabuchi , Takeshi Akimoto
发明人： Katsuo Katayama , Kyoichi Komachi , Hiroshi Mabuchi , Takeshi Akimoto
IPC分类号： H01J37/32 , C23C16/00
CPC分类号： H01J37/3244 , H01J37/32192 , H01J37/32266
摘要： A microwave plasma processing system, wherein a conductor disposed for controlling the anisotropy and the acceleration energy of ions in a plasma has inside a flow path for reactant gasses and a plurality of holes through which the gasses are to be blown toward a sample holder.A microwave plasma processing system, wherein the ratio of the total area of microwave transmission holes to the area of a conductor is set to be in a range of 0.25 to 0.65.A microwave plasma processing system, wherein each microwave transmission hole formed in a conductor has a dimension in the microwave traveling direction greater than that in a direction perpendicular to the traveling direction.
摘要翻译：一种微波等离子体处理系统，其中设置用于控制等离子体中的离子的各向异性和加速能的导体内部具有用于反应物气体的流路和多个孔，气体将通过该孔流向样品保持器。微波等离子体处理系统，其中微波透射孔的总面积与导体的面积的比率设定在0.25〜0.65的范围内。微波等离子体处理系统，其中形成在导体中的每个微波传输孔的微波行进方向上的尺寸大于与行进方向垂直的方向上的尺寸。

4. 发明授权

US5529632A Microwave plasma processing system 失效
标题翻译：微波等离子体处理系统
公开(公告)号：US5529632A
公开(公告)日：1996-06-25
申请号：US490087
申请日：1995-06-13
申请人： Katsuo Katayama , Kyoichi Komachi , Hiroshi Mabuchi , Takeshi Akimoto
发明人： Katsuo Katayama , Kyoichi Komachi , Hiroshi Mabuchi , Takeshi Akimoto
IPC分类号： H05H1/46 , H01J37/32 , H01L21/205 , H01L21/302 , H01L21/3065 , C23C16/00
CPC分类号： H01J37/32504 , Y10S156/916
摘要： A microwave plasma processing system has heating means for heating the wall of a reaction chamber, and an adhesion preventing member in which a cylinder disposed so as to be in contact with the inner face of a wall of the reaction chamber and a microwave reflecting plate having a gas discharge hole are integrally formed.A microwave plasma processing system has heating means for heating the wall of a reaction chamber, and a microwave reflecting plate which is attached to the inner face of a wall of the reaction chamber and which has a gas discharge hole.
摘要翻译：微波等离子体处理系统具有用于加热反应室的壁的加热装置和其中设置成与反应室的壁的内表面接触的圆筒和具有微波反射板的微波反射板的防粘接构件，气体排出孔一体形成。微波等离子体处理系统具有用于加热反应室的壁的加热装置和附接到反应室的壁的内表面并具有气体排出孔的微波反射板。

5. 发明申请

US20090137114A1 METHOD OF MAKING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20090137114A1
公开(公告)日：2009-05-28
申请号：US12273795
申请日：2008-11-19
申请人： Katsuhiro Uesugi , Katsuo Katayama , Katsuhisa Sakai
发明人： Katsuhiro Uesugi , Katsuo Katayama , Katsuhisa Sakai
IPC分类号： H01L21/441
CPC分类号： H01L21/76802 , H01L21/76829 , H01L21/76834
摘要： A semiconductor device is manufactured by a method including forming a first interlayer insulating film. A first etching stopper film is formed on the first interlayer insulating film. A conductive layer is formed on the first etching stopper film. A second etching stopper film is formed to cover the conductive layer, an upper surface of the conductive layer and both side surfaces of the conductive layer. A second interlayer insulating film is formed on the second etching stopper film. A hole is formed penetrating the second interlayer insulating film in a direction of thickness and reaching the conductive layer. An interconnect is formed in the hole. The step of forming a hole includes etching the second interlayer insulating film under a first etching condition, and etching the second etching stopper film under a second etching condition different from the first etching condition. The second etching condition includes using an etching gas containing C, F, and H.
摘要翻译：通过包括形成第一层间绝缘膜的方法制造半导体器件。第一蚀刻停止膜形成在第一层间绝缘膜上。在第一蚀刻停止膜上形成导电层。形成第二蚀刻阻挡膜以覆盖导电层，导电层的上表面和导电层的两个侧表面。在第二蚀刻停止膜上形成第二层间绝缘膜。在厚度方向上穿过第二层间绝缘膜并到达导电层的孔。在孔中形成互连。形成孔的步骤包括在第一蚀刻条件下蚀刻第二层间绝缘膜，并且在与第一蚀刻条件不同的第二蚀刻条件下蚀刻第二蚀刻阻挡膜。第二蚀刻条件包括使用含有C，F和H的蚀刻气体。

6. 发明授权

US5911852A Plasma processing apparatus 失效
标题翻译：等离子体处理装置
公开(公告)号：US5911852A
公开(公告)日：1999-06-15
申请号：US663640
申请日：1996-06-14
申请人： Katsuo Katayama , Kyouichi Komachi , Kouichi Iio , Takeshi Akimoto
发明人： Katsuo Katayama , Kyouichi Komachi , Kouichi Iio , Takeshi Akimoto
IPC分类号： H05H1/46 , C23C14/35 , C23F4/00 , H01J37/32 , H01L21/203 , H01L21/302 , H01L21/3065 , C23F1/08
CPC分类号： H01J37/32229 , H01J37/32192 , H01J37/32238 , H01J37/32266
摘要： A plasma processing apparatus includes a conductive thin film provided on a surface of a microwave introducing member which is exposed to a processing chamber, in which an object to be processed is placed. The conductive thin film is provided at the entire portion excluding a transmission portion, through which microwaves pass into the processing chamber. The conductive thin film is grounded to act as an electrode.
摘要翻译：等离子体处理装置包括设置在微波导入部件的表面上的导电性薄膜，所述导电薄膜暴露于放置有被处理物体的处理室。导电薄膜设置在除了传输部分之外的整个部分，微波通过该传输部分进入处理室。导电薄膜接地以作为电极。

7. 发明授权

US07465662B2 Method of making semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07465662B2
公开(公告)日：2008-12-16
申请号：US11907438
申请日：2007-10-12
申请人： Katsuhiro Uesugi , Katsuo Katayama , Katsuhisa Sakai
发明人： Katsuhiro Uesugi , Katsuo Katayama , Katsuhisa Sakai
IPC分类号： H01L21/44
CPC分类号： H01L21/76802 , H01L21/76829 , H01L21/76834
摘要： A semiconductor device is manufactured by a method including forming a first interlayer insulating film. A first etching stopper film is formed on the first interlayer insulating film. A conductive layer is formed on the first etching stopper film. A second etching stopper film is formed to cover the conductive layer, an upper surface of the conductive layer and both side surfaces of the conductive layer. A second interlayer insulating film is formed on the second etching stopper film. A hole is formed penetrating the second interlayer insulating film in a direction of thickness and reaching the conductive layer. An interconnect is formed in the hole. The step of forming a hole includes etching the second interlayer insulating film under a first etching condition, and etching the second etching stopper film under a second etching condition different from the first etching condition.
摘要翻译：通过包括形成第一层间绝缘膜的方法制造半导体器件。第一蚀刻停止膜形成在第一层间绝缘膜上。在第一蚀刻停止膜上形成导电层。形成第二蚀刻阻挡膜以覆盖导电层，导电层的上表面和导电层的两个侧表面。在第二蚀刻停止膜上形成第二层间绝缘膜。在厚度方向上穿过第二层间绝缘膜并到达导电层的孔。在孔中形成互连。形成孔的步骤包括在第一蚀刻条件下蚀刻第二层间绝缘膜，并且在与第一蚀刻条件不同的第二蚀刻条件下蚀刻第二蚀刻阻挡膜。

8. 发明申请

US20080045006A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20080045006A1
公开(公告)日：2008-02-21
申请号：US11907438
申请日：2007-10-12
申请人： Katsuhiro Uesugi , Katsuo Katayama , Katsuhisa Sakai
发明人： Katsuhiro Uesugi , Katsuo Katayama , Katsuhisa Sakai
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76829 , H01L21/76834
摘要： An etching stopper film is formed on an interlayer insulating film. A conductive layer is formed on the etching stopper film. An etching stopper film is formed to cover the conductive layer. An interlayer insulating film is formed on the etching stopper film. In a structure above, initially, a hole vertically penetrating the interlayer insulating film for exposing a surface of the etching stopper film is formed under a first etching condition. Thereafter, the etching stopper film serving as a bottom surface of the hole is removed under a second etching condition, thereby forming the hole reaching the conductive layer. An interconnection is embedded in the hole. A semiconductor device in which a hole reaching the conductive layer is prevented from extending as far as the lower interlayer insulating film as a result of misalignment, as well as a manufacturing method thereof are thus obtained.
摘要翻译：在层间绝缘膜上形成蚀刻停止膜。在蚀刻停止膜上形成导电层。形成蚀刻停止膜以覆盖导电层。在蚀刻停止膜上形成层间绝缘膜。在上述结构中，首先在第一蚀刻条件下形成垂直贯穿层间绝缘膜的用于暴露蚀刻阻挡膜的表面的孔。此后，在第二蚀刻条件下去除用作孔底的蚀刻阻挡膜，从而形成到达导电层的孔。孔中嵌有互连。由此，能够防止到达导电层的空穴的延伸到作为未对准的下层间绝缘膜的半导体装置及其制造方法。

9. 发明申请

US20060063372A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060063372A1
公开(公告)日：2006-03-23
申请号：US11229550
申请日：2005-09-20
申请人： Katsuhiro Uesugi , Katsuo Katayama , Katsuhisa Sakai
发明人： Katsuhiro Uesugi , Katsuo Katayama , Katsuhisa Sakai
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76829 , H01L21/76834
摘要： An etching stopper film is formed on an interlayer insulating film. A conductive layer is formed on the etching stopper film. An etching stopper film is formed to cover the conductive layer. An interlayer insulating film is formed on the etching stopper film. In a structure above, initially, a hole vertically penetrating the interlayer insulating film for exposing a surface of the etching stopper film is formed under a first etching condition. Thereafter, the etching stopper film serving as a bottom surface of the hole is removed under a second etching condition, thereby forming the hole reaching the conductive layer. An interconnection is embedded in the hole. A semiconductor device in which a hole reaching the conductive layer is prevented from extending as far as the lower interlayer insulating film as a result of misalignment, as well as a manufacturing method thereof are thus obtained.
摘要翻译：在层间绝缘膜上形成蚀刻停止膜。在蚀刻停止膜上形成导电层。形成蚀刻停止膜以覆盖导电层。在蚀刻停止膜上形成层间绝缘膜。在上述结构中，首先在第一蚀刻条件下形成垂直贯穿层间绝缘膜的用于暴露蚀刻阻挡膜的表面的孔。此后，在第二蚀刻条件下去除用作孔底的蚀刻阻挡膜，从而形成到达导电层的孔。孔中嵌有互连。由此，能够防止到达导电层的空穴的延伸到作为未对准的下层间绝缘膜的半导体装置及其制造方法。

10. 发明授权

US6091045A Plasma processing apparatus utilizing a microwave window having a thinner inner area 失效
标题翻译：利用具有较薄内部区域的微波窗口的等离子体处理装置
公开(公告)号：US6091045A
公开(公告)日：2000-07-18
申请号：US952779
申请日：1997-11-26
申请人： Hiroshi Mabuchi , Junya Tsuyuguchi , Katsuo Katayama , Toshihiro Hayami , Hideo Ida , Tomomi Murakami , Naohiko Takeda
发明人： Hiroshi Mabuchi , Junya Tsuyuguchi , Katsuo Katayama , Toshihiro Hayami , Hideo Ida , Tomomi Murakami , Naohiko Takeda
IPC分类号： B05D7/24 , C23C16/44 , C23C16/511 , H01J37/32 , B23K10/00
CPC分类号： B05D1/62 , C23C16/4401 , C23C16/511 , H01J37/32192 , H01J37/32238 , H01J2237/022
摘要： A plasma processing apparatus and a plasma processing method used in etching, ashing, CVD, etc. in the manufacturing, etc. of large-scale integrated circuits (LSIs) and liquid crystal display panels (LCDs). The plasma processing apparatus includes a dielectric plate used for the passage of a microwave, a microwave window disposed to confront the dielectric plate, and a reaction chamber in which a sample stage is disposed to confront the microwave window. The apparatus is characterized in that the microwave window has a recess in the area confronting the sample stage. The plasma processing method is characterized by implementing a plasma process for a sample with the plasma processing apparatus. The method and apparatus are capable of raising the plasma density in the area confronting the sample, improving the plasma processing rate, improving the etch-through performance for fine hole patterns, and improving the yield of semiconductor devices.
摘要翻译： PCT No.PCT / JP97 / 01071 Sec。 371日期：1997年11月26日 102（e）日期1997年11月26日PCT 1997年3月27日PCT公布。公开号WO97 / 36462 日期1997年10月2日在大型集成电路（LSI）和液晶显示面板（LCD）的制造等中的蚀刻，灰化，CVD等中使用的等离子体处理装置和等离子体处理方法。等离子体处理装置包括用于微波通过的电介质板，设置为面对电介质板的微波窗口，以及反射室，其中设置样品台以面对微波窗口。该装置的特征在于，微波窗口在面向样品台的区域中具有凹槽。等离子体处理方法的特征在于用等离子体处理装置对样品进行等离子体处理。该方法和装置能够提高样品面积的等离子体密度，提高等离子体处理速度，提高细孔图案的蚀刻性能，提高半导体器件的成品率。

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