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    • 2. 发明授权
      US5546363A Clock apparatus for forming time information for use in computer system 失效
    • Clock apparatus for forming time information for use in computer system
    • 用于形成用于计算机系统的时间信息的时钟装置
    • US5546363A
    • 1996-08-13
    • US358725
    • 1994-12-19
    • Jun Funaki , Shoji Tenma
    • Jun Funaki , Shoji Tenma
    • G06F1/14 , G04G3/02 , G04G7/00 , G04B17/12
    • G04G3/02 , G04G7/00
    • A commercially available clock IC which is easily influenced by a temperature change or the like is used as it is, thereby easily allowing the clock IC to function as a high precision clock IC. A high precision oscillator is provided separately from a clock circuit as a clock IC. On the basis of a clock signal from the high precision oscillator, a predetermined time, for example, one minute is measured by a high precision clock control circuit. A correction signal is transmitted to the clock circuit as a clock IC from a high precision control circuit every measurement of such a predetermined time, thereby allowing the correcting operation of the time information to be executed. The clock circuit is, consequently, made operative at a precision of the high precision oscillating circuit.
    • 容易受到温度变化等的影响的市售时钟IC被直接使用，由此容易地使时钟IC用作高精度时钟IC。 与作为时钟IC的时钟电路分开提供高精度振荡器。 基于来自高精度振荡器的时钟信号，通过高精度时钟控制电路测量例如1分钟的预定时间。 校正信号作为来自高精度控制电路的时钟IC作为时钟电路每测量一次这样的预定时间，从而允许执行时间信息的校正操作。 因此，时钟电路以高精度振荡电路的精度工作。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US5737573A Asynchronous access system having an internal buffer control circuit which invalidates an internal buffer 失效
    • Asynchronous access system having an internal buffer control circuit which invalidates an internal buffer
    • 具有使内部缓冲器无效的内部缓冲器控制电路的异步访问系统
    • US5737573A
    • 1998-04-07
    • US733721
    • 1996-10-16
    • Jun Funaki , Akira Kabemoto , Hirohide Sugahara
    • Jun Funaki , Akira Kabemoto , Hirohide Sugahara
    • G06F15/16 , G06F12/00 , G06F12/08 , G06F12/16 , G06F13/36 , G06F15/177 , G06F12/12
    • G06F12/0815
    • An asynchronous access system includes a system bus, at least one processing module provided with a main memory, a central processing unit and a first connection unit which connects to the system bus, and at least one shared memory module provided with a shared memory unit and a second connection unit which connects to the system bus. The first connection unit within the processing module makes a block read request to the shared memory module via the system bus when the first connection unit recognizes a read from the shared memory module requested from the central processing unit. The first connection unit within the processing module comprises an internal bus, an internal buffer storing data read from the shared memory module, a system bus control circuit coupled to the system bus, an internal bus control circuit coupled to the central processing unit via the internal bus, and an internal buffer control circuit controlling write/read of the internal buffer based on a signal from the internal bus control circuit. One of the internal buffer control circuit and the internal bus control circuit invalidates a content of the internal buffer when one of a plurality of invalidating conditions is satisfied.
    • 异步访问系统包括系统总线，至少一个具有主存储器的处理模块，中央处理单元和连接到系统总线的第一连接单元，以及至少一个设有共享存储单元的共享存储器模块， 连接到系统总线的第二连接单元。 当第一连接单元识别从中央处理单元请求的共享存储器模块的读取时，处理模块内的第一连接单元经由系统总线向共享存储器模块发送块读请求。 处理模块内的第一连接单元包括内部总线，存储从共享存储器模块读取的数据的内部缓冲器，耦合到系统总线的系统总线控制电路，经由内部耦合到中央处理单元的内部总线控制电路 总线和内部缓冲器控制电路，其基于来自内部总线控制电路的信号来控制内部缓冲器的写入/读取。 当满足多个无效条件中的一个时，内部缓冲器控制电路和内部总线控制电路之一使内部缓冲器的内容无效。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US5761728A Asynchronous access system controlling processing modules making requests to a shared system memory 失效
    • Asynchronous access system controlling processing modules making requests to a shared system memory
    • 控制处理模块的异步访问系统向共享系统存储器发出请求
    • US5761728A
    • 1998-06-02
    • US777184
    • 1996-12-27
    • Hiroshi Saito , Takatsugu Sasaki , Hirohide Sugahara , Akira Kabemoto , Hajime Takahashi , Jun Funaki
    • Hiroshi Saito , Takatsugu Sasaki , Hirohide Sugahara , Akira Kabemoto , Hajime Takahashi , Jun Funaki
    • G06F12/00 , G06F13/16 , G06F15/16 , G06F9/38
    • G06F13/1673
    • An asynchronous access system for a computer system includes processing modules performing processes, at least one shared system memory module, and a system bus connecting the processing modules and the shared system memory module. Each of the processing modules includes a processor, a plurality of buffers coupled to the processor and to the system bus, and a controlling unit for writing data from the plurality of processors into the shared system memory module. Data is written into the shared system memory module by a processor generating write instructions to write data via the plurality of buffers and the system bus. The controlling unit controls the writing such that one writing instruction writes data into a plurality of buffers, then transfers the data to the shared system memory module via the system bus, with another writing instruction writing additional data into another plurality of buffers and transferring the additional data to the shared system memory module.
    • 用于计算机系统的异步访问系统包括执行处理的处理模块，至少一个共享系统存储器模块以及连接处理模块和共享系统存储器模块的系统总线。 每个处理模块包括处理器，耦合到处理器和系统总线的多个缓冲器，以及用于将数据从多个处理器写入共享系统存储器模块的控制单元。 通过处理器将数据写入共享系统存储器模块，该处理器产生写入指令以经由多个缓冲器和系统总线写入数据。 控制单元控制写入，使得一个写入指令将数据写入多个缓冲器，然后经由系统总线将数据传送到共享系统存储器模块，另一个写入指令将另外的数据写入另一个多个缓冲器并传送附加的数据 数据到共享系统内存模块。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 10. 发明授权
      US5796996A Processor apparatus and its control method for controlling a processor having a CPU for executing an instruction according to a control program 失效
    • Processor apparatus and its control method for controlling a processor having a CPU for executing an instruction according to a control program
    • 用于控制具有CPU的处理器的处理器装置及其控制方法，所述处理器具有根据控制程序执行指令的CPU
    • US5796996A
    • 1998-08-18
    • US502351
    • 1995-07-14
    • Shoji Temma , Jun Funaki
    • Shoji Temma , Jun Funaki
    • G06F12/16 , G06F9/38 , G06F9/48 , G06F12/08 , G06F12/00
    • G06F9/3861 , G06F9/3834
    • In the case where a CPU executes a write instruction of a control program for a memory mapped register of an external memory, a write address and write data are written into an output buffer, thereby completing the write instruction. Prior to executing a read instruction subsequent to the write instruction, the write address and the write data of the output buffer are transferred to a sync buffer and are stored into a write address holding register and a write data holding register. Further, a using state display register is set into the holding state. When the CPU executes the read instruction, the write data of the write data holding register is written into the memory mapped register and the end of the writing operation is synchronized with the end of the read instruction. When the sync buffer unit receives an interruption instruction in the holding state, an interruption return instruction address is returned to an address of the write instruction of the data in the holding state. The process is restarted from the write instruction of the memory mapped register by the control program by the end of the interruption.
    • 在CPU执行外部存储器的存储器映射寄存器的控制程序的写入指令的情况下，将写入地址和写入数据写入输出缓冲器，从而完成写入指令。 在执行写入指令之后的读取指令之前，将输出缓冲器的写入地址和写入数据传送到同步缓冲器，并将其存储到写入地址保持寄存器和写入数据保持寄存器中。 此外，将使用状态显示寄存器设置为保持状态。 当CPU执行读取指令时，写入数据保持寄存器的写入数据被写入存储器映射寄存器，并且写入操作的结束与读取指令的结束同步。 当同步缓冲器单元接收到处于保持状态的中断指令时，中断返回指令地址返回到保持状态下的数据的写入指令的地址。 在中断结束时，控制程序从存储器映射寄存器的写入指令重新开始该过程。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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