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1. 发明授权

US5170245A Semiconductor device having metallic interconnects formed by grit blasting 失效
标题翻译：具有通过喷砂形成的金属互连的半导体装置
公开(公告)号：US5170245A
公开(公告)日：1992-12-08
申请号：US653978
申请日：1991-02-11
申请人： Jungihl Kim , Joseph C. Logue , John J. Ritsko , Robert R. Shaw , George F. Walker
发明人： Jungihl Kim , Joseph C. Logue , John J. Ritsko , Robert R. Shaw , George F. Walker
IPC分类号： B24C1/04 , B24C3/32 , H01L21/48 , H05K1/03 , H05K3/00
CPC分类号： H01L21/4807 , B24C1/04 , B24C3/322 , H01L21/486 , H05K3/0044 , H05K1/0306 , H05K2203/025 , H05K3/4629
摘要： This invention relates to a ceramic module and to methods for forming protruding, upstanding electrically conducting pins by the selective abrasion of a surface 18 of a multilayered ceramic module 10. An abrasive blasting device 40 is disposed adjacent to the surface 18 for directing a stream of abrasive particles 42 against the surface. The particles 42 strike both metallic conductors 20 and 22 and also the ceramic material of the layer 14. Inasmuch as the ceramic material is relatively hard and brittle as compared to the ductile metallic conductors the abrasive particles 42 abrade away the ceramic layer 14 at a faster rate than the ductile metallic material of the conductors 20 and 22. The abrasive particles 42 may be comprised of any suitable abrasive, such as Al.sub.2 O.sub.3, SiC or WC. The module may be rotated beneath a nozzle of the grit blasting device, the nozzle being linearly translated above the surface being abraded.
摘要翻译：本发明涉及一种陶瓷模块以及通过多层陶瓷模块10的表面18的选择性磨损来形成突出的，直立的导电销的方法。喷砂装置40邻近表面18设置，用于引导研磨颗粒42抵靠表面。颗粒42撞击金属导体20和22以及层14的陶瓷材料。由于与延性金属导体相比，陶瓷材料相对硬且脆，研磨颗粒42以更快的速度磨掉陶瓷层14 导体20和22的韧性金属材料的比率。磨料颗粒42可以由任何合适的研磨剂，例如Al 2 O 3，SiC或WC组成。模块可以在喷砂装置的喷嘴下方旋转，喷嘴在被磨损的表面上线性平移。

2. 发明授权

US4802099A Physical parameter balancing of circuit islands in integrated circuit wafers 失效
标题翻译：集成电路晶圆中电路岛的物理参数平衡
公开(公告)号：US4802099A
公开(公告)日：1989-01-31
申请号：US816093
申请日：1986-01-03
申请人： Joseph C. Logue
发明人： Joseph C. Logue
IPC分类号： H01L21/822 , H01L21/66 , H01L21/82 , H01L25/065 , H01L27/02 , H01L27/04 , H01L27/118 , G06F15/60
CPC分类号： H01L25/0657 , H01L27/0211 , H01L27/118 , H01L2225/06513 , H01L2225/06589 , H01L2225/06596 , H01L2924/0002
摘要： Balancing values of physical parameters such as temperature between used and unused circuit islands, in a fault bypass wafer circuit module, is done by mandating circuit exercise within each island considered critical. Within individual exercise islands, thermostats control heaters, or other physical parameter reporting means control transducers to return the physical parameter to nominal values. Heavily exercised operational islands and unexercised faulty or good redundant islands, which could develop destructive thermal gradients and resulting operational or connection failures. To eliminate such physical gradients, circuit exercise is mandated in all circuit islands which receive no ordinary circuit exercise, simply to maintain physical balance. Temperature is the physical parameter of primary concern, but physical parameters include piezoelectric effects, capacitance, inductance, magnetism, radiation effects and voltage, as well as other physical parameters which may be related or derivative. Each island of concern as a critical exercise island is equipped with physical parameter balancing means, comprising a physical parameter sensor and transducer controlled by the sensor to alter that physical parameter. The physical parameter may be measured, may be detected at a threshold, or may be calculated by interference from exercise event counts. The counts may be taken externally in a computer, or internally by configuring an event counter within the electronics of the island. An interposer and a conductive liquid for combined electrical and heat distribution are options.
摘要翻译：在故障旁路晶片电路模块中，平衡物理参数（例如使用的和未使用的电路岛之间的温度）的值是通过在每个被认为是关键的岛内的电路运行来实现的。在单独的运动岛内，恒温器控制加热器或其他物理参数报告装置控制换能器将物理参数返回到标称值。重新操作岛屿和未经过修复的故障或冗余的岛屿，这可能会产生破坏性的热梯度并导致操作或连接故障。为了消除这种物理梯度，在所有电路岛中规定电路运行，这些岛不接受普通的电路运动，只需维持物理平衡。温度是主要关注的物理参数，但物理参数包括压电效应，电容，电感，磁性，辐射效应和电压，以及可能相关或衍生的其他物理参数。作为关键运动岛的每个岛屿都配备有物理参数平衡装置，其包括物理参数传感器和由传感器控制的换能器以改变该物理参数。可以测量物理参数，可以在阈值处检测，或者可以通过运动事件计数的干扰来计算。计数可以在计算机外部进行，也可以在内部通过在岛内的电子设备中配置事件计数器。用于组合电和热分布的插入器和导电液体是选项。

3. 发明授权

US4034356A Reconfigurable logic array 失效
标题翻译：可重构逻辑阵列
公开(公告)号：US4034356A
公开(公告)日：1977-07-05
申请号：US637261
申请日：1975-12-03
申请人： Frank E. Howley , John W. Jones , Joseph C. Logue
发明人： Frank E. Howley , John W. Jones , Joseph C. Logue
IPC分类号： G06F7/00 , G01R31/3185 , H03K19/177 , G11C11/36
CPC分类号： G01R31/318516 , H03K19/1772
摘要： This specification describes a set of arrays for performing logic function in various subsets of the original set. The array structure is characterized by a plurality of arrays joined together with a bidirectional bussing system. This bussing system comprises addressing lines of the arrays joined together by switching circuitry used to regroup the set into subsets as necessary to perform the logic functions.
摘要翻译：该规范描述了用于在原始集合的各种子集中执行逻辑功能的一组数组。阵列结构的特征在于与双向总线系统连接在一起的多个阵列。该总线系统包括通过用于将集合重组为子集的开关电路来连接到一起的阵列的线，以执行逻辑功能。

4. 发明授权

US4896464A Formation of metallic interconnects by grit blasting 失效
标题翻译：通过喷砂形成金属互连
公开(公告)号：US4896464A
公开(公告)日：1990-01-30
申请号：US207085
申请日：1988-06-15
申请人： Jungihl Kim , Joseph C. Logue , John J. Ritsko , Robert R. Shaw , George F. Walker
发明人： Jungihl Kim , Joseph C. Logue , John J. Ritsko , Robert R. Shaw , George F. Walker
IPC分类号： H01L23/50 , B24C1/04 , B24C3/32 , H01L21/48 , H05K1/03 , H05K3/00 , H05K3/46
CPC分类号： H01L21/486 , B24C1/04 , B24C3/322 , H01L21/4807 , H05K3/0044 , H05K1/0306 , H05K2203/025 , H05K3/4629
摘要： This invention relates to a ceramic module and to methods for forming protruding, upstanding electrically conducting pins by the selective abrasion of a surface 18 of a multilayered ceramic module 10. An abrasive blasting device 40 is disposed adjacent to the surface 18 for directing a stream of abrasive particles 42 against the surface. The particles 42 strike both metallic conductors 20 and 22 and also the ceramic material of the layer 14. Inasmuch as the ceramic material is relatively hard and brittle as compared to the ductile metallic conductors the abrasive particles 42 abrade away the ceramic layer 14 at a faster rate than the ductile metallic material of the conductors 20 and 22. The abrasive particles 42 may be comprised of any suitable abrasive, such as Al.sub.2 O.sub.3, SiC or WC. The module may be rotated beneath a nozzle of the grit blasting device, the nozzle being linearly translated above the surface being abraded.

5. 发明授权

US4268908A Modular macroprocessing system comprising a microprocessor and an extendable number of programmed logic arrays 失效
标题翻译：模块化宏处理系统包括微处理器和可扩展数量的编程逻辑阵列
公开(公告)号：US4268908A
公开(公告)日：1981-05-19
申请号：US15505
申请日：1979-02-26
申请人： Joseph C. Logue , Wei-Wha Wu
发明人： Joseph C. Logue , Wei-Wha Wu
IPC分类号： G06F7/00 , G06F9/22 , G06F9/30 , G06F13/12 , G06F15/78
CPC分类号： G06F15/7864 , G06F9/223 , G06F9/226
摘要： A modular system comprising a microprocessor having a system bus (control address and data) and one or more programmed logic arrays connected to said system bus. Three system configurations are shown by way of example, Macroprocessor, Peripheral Input/Output and Direct Memory Access applications. The microprocessor executes a standard set of instructions and addresses each programmed logic array. Each array executes a specific instruction, beyond the standard set of instructions, upon receipt of its address.
摘要翻译：一种模块化系统，包括具有系统总线（控制地址和数据）和连接到所述系统总线的一个或多个编程逻辑阵列的微处理器。三个系统配置通过示例显示，大型处理器，外设输入/输出和直接存储器访问应用程序。微处理器执行一组标准的指令，并对每个编程的逻辑阵列进行寻址。每个阵列在接收到其地址后，执行超出标准指令集的特定指令。

6. 发明授权

US3984860A Multi-function LSI wafers 失效
标题翻译：多功能LSI晶圆
公开(公告)号：US3984860A
公开(公告)日：1976-10-05
申请号：US532419
申请日：1974-12-13
申请人： Joseph C. Logue
发明人： Joseph C. Logue
IPC分类号： H01L27/118 , H01L23/48 , H01L29/44 , H01L29/52 , H01L29/60
CPC分类号： H01L27/118
摘要： A system that is to be placed on a wafer is partitioned into reasonably large functions, each provided with a set of I/O and power pads. The wafer design is called "design A"0 A second wafer design (design B) that is the mirror image of design A is also constructed. Wafers of designs A and B are tested and divided into two groups: group I wafers have relatively few functions that are inoperative; group II wafers have relatively few functions that are operative. Inoperative functions are removed from group I wafers and discarded; good functions are removed from group II wafers and retained. A given function on wafer A is the mirror image of the same function on wafer B. Therefore, a given function from a group II wafer A (or B) can be inverted and attached to a group I wafer B (or A) that has had the corresponding function removed from it. The I/O and power pads of the function removed from the group II wafer are joined to the I/O and power pads remaining on the group I wafer.
摘要翻译：放置在晶片上的系统被划分成相当大的功能，每个功能都配有一组I / O和电源板。晶圆设计称为“设计A”0也是构建设计A的镜像的第二晶片设计（设计B）。设计A和B的晶片被测试并分为两组：第一组晶片具有相对较少的功能不起作用; 第二组晶片具有相对较少的功能。从I组晶片中除去不能工作的功能并丢弃; 良好的功能从第二组晶圆中取出并保留下来。晶片A上的给定功能是在晶片B上具有相同功能的镜像。因此，来自组II晶片A（或B）的给定功能可以反转并附着到具有有相应的功能从中删除。将从II组晶片去除的功能的I / O和电源焊盘连接到I组晶圆上剩余的I / O和电源板。

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